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M25P40-VMN6TP/X 参数 Datasheet PDF下载

M25P40-VMN6TP/X图片预览
型号: M25P40-VMN6TP/X
PDF下载: 下载PDF文件 查看货源
内容描述: 4兆位,低电压,串行闪存,具有50 MHz SPI总线接口 [4 Mbit, low voltage, serial Flash memory with 50 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 53 页 / 499 K
品牌: STMICROELECTRONICS [ ST ]
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M25P40  
Revision history  
Table 25. Document revision history (continued)  
Date  
Revision  
Changes  
50 MHz operation added (see Table 20: AC characteristics (50 MHz  
operation, device grade 6, VCC min = 2.7 V)). All packages are  
ECOPACK®. Blank option removed from under Plating technology in  
Table 24: Ordering information scheme. MLP package renamed as  
VFQFPN, silhouette and package mechanical drawing updated (see on  
page 1 and Figure 27: VFQFPN8 (MLP8) 8-lead Very thin Fine pitch  
Quad Flat Package No lead, 6 × 5 mm, package outline.  
24-Oct-2005  
7.0  
Note 2 added below Figure 26 and note 1 added below Figure 27  
tRES1 and tRES2 modified in Table 20: AC characteristics (50 MHz  
operation, device grade 6, VCC min = 2.7 V).  
22-Dec-2005  
8.0  
Read Identification (RDID) added. Titles of Figure 27 and Table 23  
corrected.  
The data contained in Table 11, Table 16 and Table 19 is no longer  
preliminary data.  
Figure 3: Bus Master and memory devices on the SPI bus modified and  
Note 2 added.  
40 MHz frequency condition modified for ICC3 in Table 14: DC  
characteristics (device grade 3).  
Table 16: Instruction times (device grade 3) shows preliminary data.  
14-Apr-2006  
9
Condition changed for the Data Retention parameter in Table 11: Data  
retention and endurance. VWI parameter for device grade 3 added to  
Table 8: Power-up timing and VWI threshold.  
SO8 package specifications updated (see Figure 26 and Table 22).  
/X Process added to Table 24: Ordering information scheme.  
tRES1 and tRES2 parameter timings changed for devices produced with the  
“X” process technology in Table 19 and Table 19.  
05-Jun-2006  
18-Dec-2006  
10  
11  
SO8 Narrow package specifications updated (see Figure 26 and  
Table 22).  
Hardware Write Protection feature added on page 1. Small text changes.  
Section 2.7: VCC supply voltage and Section 2.8: VSS ground added.  
Figure 3: Bus Master and memory devices on the SPI bus modified,  
note 2 removed and replaced by explanatory paragraph.  
WIP bit behavior specified at Power-up in Section 7: Power-up and  
Power-down. TLEAD added to Table 9: Absolute maximum ratings and VIO  
max modified.  
VFQFPN8 package specifications updated (see Table 23 and Figure 27).  
VCC voltage range from W17 2007 is extended to 2.3 V to 3.6 V.  
Table 21: AC characteristics (33 MHz operation, device grade 6, VCCmin  
=2.3 V) added.  
25-Jan-2007  
12  
Table 18: Which AC characteristics to use? added. AC characteristics at  
40 MHz removed.  
51/53  
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