M24C64, M24C32
Figure 10. Read Mode Sequences
ACK
CURRENT
ADDRESS
READ
START
DEV SEL
R/W
NO ACK
DATA OUT
STOP
ACK
ACK
RANDOM
ADDRESS
READ
START
DEV SEL *
R/W
ACK
DEV SEL *
START
ACK
NO ACK
DATA OUT
STOP
ACK
BYTE ADDR
BYTE ADDR
R/W
ACK
SEQUENTIAL
CURRENT
READ
START
DEV SEL
R/W
ACK
ACK
NO ACK
DATA OUT 1
DATA OUT N
STOP
ACK
SEQUENTIAL
RANDOM
READ
START
DEV SEL *
ACK
ACK
DEV SEL *
START
ACK
BYTE ADDR
R/W
BYTE ADDR
DATA OUT 1
R/W
ACK
NO ACK
DATA OUT N
STOP
AI01105C
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
st
and 4
th
bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
After the successful completion of a Read opera-
tion, the device’s internal address counter is incre-
mented by one, to point to the next byte address.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in
but
without
sending a Stop condition.
Then, the bus master sends another Start condi-
tion, and repeats the Device Select Code, with the
Read/Write bit (RW) set to 1. The device acknowl-
edges this, and outputs the contents of the ad-
12/26
dressed byte. The bus master must
not
acknowledge the byte, and terminates the transfer
with a Stop condition.
Current Address Read
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the Read/Write bit (RW) set
to 1. The device acknowledges this, and outputs
the byte addressed by the internal address
counter. The counter is then incremented. The bus
master terminates the transfer with a Stop condi-
tion, as shown in
without
acknowledg-
ing the byte.
STMICROELECTRONICS [ STMICROELECTRONICS ]
