M24C64, M24C32
Figure 8. Read Mode Sequences
ACK
CURRENT
ADDRESS
READ
START
DEV SEL
R/W
NO ACK
DATA OUT
STOP
ACK
ACK
RANDOM
ADDRESS
READ
START
DEV SEL *
R/W
ACK
DEV SEL *
START
ACK
NO ACK
DATA OUT
STOP
ACK
BYTE ADDR
BYTE ADDR
R/W
ACK
SEQUENTIAL
CURRENT
READ
START
DEV SEL
R/W
ACK
ACK
NO ACK
DATA OUT 1
DATA OUT N
STOP
ACK
SEQUENTIAL
RANDOM
READ
START
DEV SEL *
ACK
ACK
DEV SEL *
START
ACK
BYTE ADDR
R/W
BYTE ADDR
DATA OUT 1
R/W
ACK
NO ACK
DATA OUT N
STOP
AI01105C
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
st
and 4
th
bytes) must be identical.
internal address counter. The counter is then in-
cremented. The master terminates the transfer
with a STOP condition, as shown in Figure 8,
with-
out
acknowledging the byte output.
Sequential Read
This mode can be initiated with either a Current
Address Read or a Random Address Read. The
master
does
acknowledge the data byte output in
this case, and the memory continues to output the
next byte in sequence. To terminate the stream of
bytes, the master must
not
acknowledge the last
byte output, and
must
generate a STOP condition.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’
and the memory continues to output data from
memory address 00h.
Acknowledge in Read Mode
In all read modes, the memory waits, after each
byte read, for an acknowledgment during the 9
th
bit time. If the master does not pull the SDA line
low during this time, the memory terminates the
data transfer and switches to its stand-by state.
9/19
STMICROELECTRONICS [ STMICROELECTRONICS ]
