M24C16, M24C08, M24C04, M24C02, M24C01
Figure 9. Read Mode Sequences
ACK
CURRENT
ADDRESS
READ
START
DEV SEL
R/W
NO ACK
DATA OUT
STOP
ACK
DEV SEL *
START
R/W
ACK
RANDOM
ADDRESS
READ
START
DEV SEL *
R/W
ACK
NO ACK
DATA OUT
STOP
NO ACK
ACK
AI01942
BYTE ADDR
ACK
SEQUENTIAL
CURRENT
READ
START
DEV SEL
R/W
ACK
ACK
DATA OUT 1
DATA OUT N
STOP
ACK
SEQUENTIAL
RANDOM
READ
START
DEV SEL *
R/W
ACK
DEV SEL *
START
ACK
BYTE ADDR
DATA OUT 1
R/W
ACK
NO ACK
DATA OUT N
STOP
Note: The seven most significant bits of the Device Select Code of a Random Read (in the 1
st
and 3
rd
bytes) must be identical.
Read Operations
Read operations are performed independently of
the state of the Write Control (WC) signal.
The device has an internal address counter which
is incremented each time a byte is read.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in
but
without
sending a Stop condition. Then,
the bus master sends another Start condition, and
repeats the Device Select Code, with the RW bit
set to 1. The device acknowledges this, and out-
puts the contents of the addressed byte. The bus
master must
not
acknowledge the byte, and termi-
nates the transfer with a Stop condition.
Current Address Read
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the RW bit set to 1. The de-
vice acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master ter-
minates the transfer with a Stop condition, as
shown in
without
acknowledging the
byte.
11/29
STMICROELECTRONICS [ STMICROELECTRONICS ]
