M24C16, M24C08, M24C04, M24C02, M24C01
Table 13. AC Characteristics (M24Cxx-W)
Test conditions specified in Table 6. and Table 11.
Parameter
Symbol
fC
Alt.
fSCL
Min.
Max.
Unit
kHz
ns
Clock Frequency
400
tCHCL
tCLCH
tHIGH
tLOW
tF
Clock Pulse Width High
Clock Pulse Width Low
SDA Fall Time
600
1300
20
ns
2
300
900
ns
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
100
0
ns
ns
200
200
600
600
600
1300
ns
3
tAA
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
ns
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
tBUF
ns
ns
ns
ns
ms
tCHDX
tDLCL
tCHDH
tDHDL
Start Condition Hold Time
Stop Condition Set Up Time
Time between Stop Condition and Next Start Condition
Write Time
4
tWR
5
tW
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. Previous devices bearing the process letter “L” in the package marking guarantee a maximum write time of 10ms. For more infor-
mation about these devices and their device identification, please ask your ST Sales Office for Process Change Notices PCN MPG/
EE/0061 and 0062 (PCEE0061 and PCEE0062).
Table 14. AC Characteristics (M24Cxx-R)
Test conditions specified in Table 7. and Table 10.
4
4
Symbol
fC
Alt.
fSCL
Parameter
Unit
kHz
ns
Min.
Max.
Clock Frequency
400
tCHCL
tCLCH
tHIGH
tLOW
tF
Clock Pulse Width High
Clock Pulse Width Low
SDA Fall Time
600
1300
20
ns
2
300
900
ns
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
100
0
ns
ns
200
200
600
600
600
1300
ns
3
tAA
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
ns
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
tBUF
ns
tCHDX
tDLCL
tCHDH
tDHDL
tW
Start Condition Hold Time
ns
Stop Condition Set Up Time
ns
Time between Stop Condition and Next Start Condition
Write Time
ns
tWR
10
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. This is preliminary information.
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