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M24C02-WMN6TP 参数 Datasheet PDF下载

M24C02-WMN6TP图片预览
型号: M24C02-WMN6TP
PDF下载: 下载PDF文件 查看货源
内容描述: 16Kbit的, 8Kbit , 4k位, 2Kbit和1K位,串行I²C总线EEPROM [16Kbit, 8Kbit, 4Kbit, 2Kbit and 1Kbit Serial I2C Bus EEPROM]
分类和应用: 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 29 页 / 484 K
品牌: STMICROELECTRONICS [ STMICROELECTRONICS ]
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M24C16, M24C08, M24C04, M24C02, M24C01
Figure 6. Write Mode Sequences with WC=1 (data write inhibited)
WC
ACK
Byte Write
START
DEV SEL
R/W
ACK
NO ACK
DATA IN
STOP
ACK
NO ACK
DATA IN 1
BYTE ADDR
WC
ACK
Page Write
START
DEV SEL
R/W
NO ACK
DATA IN 3
BYTE ADDR
DATA IN 2
WC (cont'd)
NO ACK
Page Write
(cont'd)
NO ACK
DATA IN N
STOP
AI02803C
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in
and waits for an address byte. The device re-
sponds to the address byte with an acknowledge
bit, and then waits for the data byte.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10
th
bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
and Serial Clock (SCL) are ignored, and the de-
vice does not respond to any requests.
Byte Write
After the Device Select code and the address byte,
the bus master sends one data byte. If the ad-
dressed location is Write-protected, by Write Con-
trol (WC) being driven High (during the period from
the Start condition until the end of the address
byte), the device replies to the data byte with
NoAck, as shown in
and the location is
not modified. If, instead, the addressed location is
not Write-protected, the device replies with Ack.
The bus master terminates the transfer by gener-
ating a Stop condition, as shown in
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same page in the memory:
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the page, a condition known as ‘roll-
over’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If the addressed loca-
tion is Write-protected, by Write Control (WC) be-
ing driven High (during the period from the Start
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