M24128-BW, M24128-BR, M24256-BW, M24256-BR
Table 15. AC Characteristics (M24128-BR, M24256-BR)
Test conditions specified in
Symbol
f
C
t
CHCL
t
CLCH
t
CH1CH2
t
CL1CL2
t
DH1DH2 2
t
DL1DL2 2
t
DXCX
t
CLDX
t
CLQX
t
CLQV 3
t
CHDX 1
t
DLCL
t
CHDH
t
DHDL
t
W
Alt.
f
SCL
t
HIGH
t
LOW
t
R
t
F
t
R
t
F
t
SU:DAT
t
HD:DAT
t
DH
t
AA
t
SU:STA
t
HD:STA
t
SU:STO
t
BUF
t
WR
Clock Frequency
Clock Pulse Width High
Clock Pulse Width Low
Clock Rise Time
Clock Fall Time
SDA Rise Time
SDA Fall Time
Data In Set Up Time
Data In Hold Time
Data Out Hold Time
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
Start Condition Hold Time
Stop Condition Set Up Time
Time between Stop Condition and Next Start
Condition
Write Time
20
20
100
0
200
200
600
600
600
1300
10
900
600
1300
300
300
300
300
Parameter
Min.
Max.
400
Unit
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
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