FLGA
Fine Pitch Land Grid Array
SPECIFICATIONS
Die Thickness
Mold Cap Thickness
Marking
Packing Options
75–300µm (3-12 mils)
0.25-0.90mm
Laser
Tape & reel/JEDEC tray
RELIABILITY
Moisture Sensitivity Level
Temperature Cycling
High Temp Storage
Pressure Cooker Test
Temperature/Humidity Test
Unbiased HAST
JEDEC Level 2A, 260°C Reflow
Condition C (–65°C to 150°C),
1000 cycles
150°C, 1000 hrs
121°C/100%RH/2atm, 168 hrs
85°C/85% RH, 1000 hrs
130°C/85% RH/2 atm, 96 hrs
THERMAL PERFORMANCE,
θ
ja (°C/W)
Thermal performance is highly dependent on package size, die size, substrate layers and thickness, and land configuration.
Simulation for specific applications should be performed to obtain maximum accuracy.
Package
VFLGA
Body Size (mm)
9 x 9 (4L)
Pin Count
11 2
Die Size
4.1 x 4.1
PCB Vias
16
Thermal Performance
θja(ºC/W)
36.1
Note: Simulation data for package mounted on 4 layer PCB (per JEDEC JESD51-9) under natural convection as defined in JESD51-2.
ELECTRICAL PERFORMANCE
Electrical parasitic data is highly dependent on the package layout. 3D electrical simulation can be used on the specific package design
to provide the best prediction of electrical behavior. First order approximations can be calculated using parasitics per unit length for the
constituents of the signal path. Data below is for a frequency of 100MHz and assumes 1.0 mil gold bonding wire.
Conductor
Component
Wire
Net (2L)
Total (2L)
Wire
Net (4L)
Total (4L)
Note: Net = Total Trace Length + Via
Length
(mm)
2
2-7
4-0
2
2-7
4-9
Resistance
(mOhms)
120
25 -110
145 - 230
120
25 - 110
145 - 230
Inductance
(nH)
1.65
1.10 - 4.35
2.75 - 6.00
1.65
0.70 - 2.95
2.35 - 4.60
Inductance
Mutual (nH)
0.45 - 0.85
0.25 - 2.27
0.70 - 3.12
0.45 - 0.85
0.17 - 1.57
0.62 - 2.42
Capacitance
(pF)
0.10
0.20 - 0.90
0.30 - 1.00
0.10
0.30 - 1.05
0.40 - 1.15
Capacitance
Mutual (pF)
0.01 - 0.02
0.05 - 0.41
0.06 - 0.43
0.01 - 0.02
0.05 - 0.41
0.06 - 0.43
CROSS-SECTION
FLGA
PACKAGE CONFIGURATIONS
Body Sizes (mm)
4x4 to 13x13
Terminal Count
8 to 200
Terminal Pitch (mm) 0.50 to 0.80
Typ. Pkg. Thickness
TFLGA: 1.20mm
VFLGA: 1.00mm max.
WFLGA: 0.80mm max.
Corporate Office
Global Offices
10 Ang Mo Kio St. 65, #05-17/20 Techpoint, Singapore 569059 Tel: 65-6824-7777 Fax: 65-6720-7823
USA 510-979-8000
JAPAN 81-3-5789-5850
KOREA 82-31-639-8911 TAIWAN 886-3-593-6565
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UK 44-1483-413-700
MALAYSIA 603-4257-6222
NETHERLANDS 31-38-333-2023
The STATS ChipPAC logo is a registered trademark of STATS ChipPAC Ltd. All other product names and other company names herein are for identification purposes only and may be the trademarks or registered trademarks
of their respective owners. STATS ChipPAC disclaims any and all rights in those marks. STATS ChipPAC makes no guarantee or warranty of its accuracy in the information given, or that the use of such information
will not infringe on intellectual rights of third parties. Under no circumstances shall STATS ChipPAC be liable for any damages whatsoever arising out of the use of, or inability to use the materials in this document.
STATS ChipPAC reserves the right to change the information at any time and without notice.
©Copyright 2006. STATS ChipPAC Ltd. All rights reserved.
May 2006
STATSCHIP [ STATS CHIPPAC, LTD. ]
