FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
V
V
DD
I
DD
I
DD
DD
V
V
V
DD
V
DD
P0
DD
P0
DD
RST
EA#
RST
EA#
SST89x516RDx
SST89x5xxRDx
XTAL2
XTAL1
XTAL2
XTAL1
(NC)
(NC)
CLOCK
SIGNAL
V
V
SS
SS
1273 F42.0
1273 F41.0
All other pins disconnected
All other pins disconnected
FIGURE 14-13: IDD Test Condition,
Power-down Mode
FIGURE 14-12: IDD Test Condition,
Idle Mode
TABLE 14-11: Flash Memory Programming/
Verification Parameters1
Parameter2
Max
150
100
30
Units
ms
ms
ms
µs
Chip-Erase Time
Block-Erase Time
Sector-Erase Time
Byte-Program Time3
Select-Block Program Time
Re-map or Security bit Program Time
50
500
80
ns
µs
T14-11.1 1273
1. For IAP operations, the program execution overhead
must be added to the above timing parameters.
2. Program and Erase times will scale inversely proportional
to programming clock frequency.
3. Each byte must be erased before programming.
©2007 Silicon Storage Technology, Inc.
S71273-03-000
1/07
76
SST [ SILICON STORAGE TECHNOLOGY, INC ]
