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SST89E516RD2-40-C-NJE 参数 Datasheet PDF下载

SST89E516RD2-40-C-NJE图片预览
型号: SST89E516RD2-40-C-NJE
PDF下载: 下载PDF文件 查看货源
内容描述: FlashFlex MCU [FlashFlex MCU]
分类和应用: 外围集成电路微控制器PC时钟
文件页数/大小: 81 页 / 832 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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FlashFlex MCU  
SST89E516RD2 / SST89E516RD  
SST89V516RD2 / SST89V516RD  
Data Sheet  
Bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) deter-  
mine whether the capture input will be active on a positive  
edge or negative edge. The CAPN bit enables the negative  
edge that a capture input will be active on, and the CAPP  
bit enables the positive edge. When both bits are set, both  
edges will be enabled and a capture will occur for either  
transition. The last bit in the register ECOM (CCAPMn.6)  
when set, enables the comparator function. Table 8-5  
shows the CCAPMn settings for the various PCA functions.  
8.3 Compare/Capture Modules  
Each PCA module has an associated SFR with it. These  
registers are: CCAPM0 for module 0, CCAPM1 for module  
1, etc. Refer to “PCA Compare/Capture Module Mode Reg-  
ister (CCAPMn)” on page 28 for details. The registers each  
contain 7 bits which are used to control the mode each  
module will operate in. The ECCF bit (CCAPMn.0 where n  
= 0, 1, 2, 3, or 4 depending on module) will enable the CCF  
flag in the CCON SFR to generate an interrupt when a  
match or compare occurs. PWM (CCAPMn.1) enables the  
pulse width modulation mode. The TOG bit (CCAPMn.2)  
when set, causes the CEX output associated with the mod-  
ule to toggle when there is a match between the PCA  
counter and the module’s capture/compare register. When  
there is a match between the PCA counter and the mod-  
ule’s capture/compare register, the MATn (CCAPMn.3) and  
the CCFn bit in the CCON register to be set.  
There are two additional register associated with each of  
the PCA modules: CCAPnH and CCAPnL. They are regis-  
ters that hold the 16-bit count value when a capture occurs  
or a compare occurs. When a module is used in PWM  
mode, these registers are used to control the duty cycle of  
the output. See Figure 8-1.  
TABLE  
8-4: PCA High and Low Register Compare/Capture Modules  
Bit Address, Symbol, or Alternative Port Function  
Direct  
Address MSB  
RESET  
Value  
Symbol Description  
LSB  
CCAP0H PCA Module 0  
FAH  
EAH  
CCAP0H[7:0]  
CCAP0L[7:0]  
00H  
00H  
Compare/Capture  
CCAP0L  
Registers  
CCAP1H PCA Module 1  
FBH  
EBH  
CCAP1H[7:0]  
CCAP1L[7:0]  
00H  
00H  
Compare/Capture  
CCAP1L  
Registers  
CCAP2H PCA Module 2  
FCH  
ECH  
CCAP2H[7:0]  
CCAP2L[7:0]  
00H  
00H  
Compare/Capture  
CCAP2L  
Registers  
CCAP3H PCA Module 3  
FDH  
EDH  
CCAP3H[7:0]  
CCAP3L[7:0]  
00H  
00H  
Compare/Capture  
CCAP3L  
Registers  
CCAP4H PCA Module 4  
FEH  
EEH  
CCAP4H[7:0]  
CCAP4L[7:0]  
00H  
00H  
Compare/Capture  
CCAP4L  
Registers  
T8-4.0 1273  
©2007 Silicon Storage Technology, Inc.  
S71273-03-000  
1/07  
48  
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