FlashFlex MCU
SST89E516RD2 / SST89E516RD
SST89V516RD2 / SST89V516RD
Data Sheet
6.2 Serial Peripheral Interface
Select Slave 3 Only
Slave 2
Given Address
Possible Addresses
6.2.1 SPI Features
1111 X0X1
1111 1011
1111 1001
•
•
•
•
•
•
•
Master or slave operation
10 MHz bit frequency (max)
LSB first or MSB first data transfer
Four programmable bit rates
End of transmission (SPIF)
Write collision flag protection (WCOL)
Wake up from idle mode (slave mode only)
The user could use the possible addresses above to select
slave 3 only. Another combination could be to select slave 2
and 3 only as shown below.
Select Slaves 2 & 3 Only
Slaves 2 & 3
Possible Addresses
6.2.2 SPI Description
1111 0011
The serial peripheral interface (SPI) allows high-speed syn-
chronous data transfer between the SST89E/V516RDx
and peripheral devices or between several SST89E/
V516RDx devices.
More than one slave may have the same SADDR address
as well, and a given address could be used to modify the
address so that it is unique.
Figure 6-4 shows the correspondence between master
and slave SPI devices. The SCK pin is the clock output and
input for the master and slave modes, respectively. The SPI
clock generator will start following a write to the master
devices SPI data register. The written data is then shifted
out of the MOSI pin on the master device into the MOSI pin
of the slave device. Following a complete transmission of
one byte of data, the SPI clock generator is stopped and
the SPIF flag is set. An SPI interrupt request will be gener-
ated if the SPI Interrupt Enable bit (SPIE) and the Serial
Port Interrupt Enable bit (ES) are both set.
6.1.2.2 Using the Broadcast Address to Select Slaves
Using the broadcast address, the master can communicate
with all the slaves at once. It is formed by performing a logi-
cal OR of SADDR and SADEN with ‘0’s in the result treated
as “don’t cares”.
Slave 1
1111 0001 = SADDR
+1111 1010 = SADEN
1111 1X11 = Broadcast
An external master drives the Slave Select input pin, SS#/
P1[4], low to select the SPI module as a slave. If SS#/P1[4]
has not been driven low, then the slave SPI unit is not
active and the MOSI/P1[5] port can also be used as an
input port pin.
“Don’t cares” allow for a wider range in defining the broad-
cast address, but in most cases, the broadcast address will
be FFH.
On reset, SADDR and SADEN are “0”. This produces an
given address of all “don’t cares” as well as a broadcast
address of all “don’t cares.” This effectively disables Auto-
matic Addressing mode and allows the microcontroller to
function as a standard 8051, which does not make use of
this feature.
CPHA and CPOL control the phase and polarity of the SPI
clock. Figures 1 and 6-5 show the four possible combina-
tions of these two bits.
MSB Master LSB
8-bit Shift Register
MSB Slave LSB
8-bit Shift Register
MISO MISO
MOSI MOSI
SCK
SS#
SCK
SS#
SPI
Clock Generator
1273 F16.0
V
V
DD
SS
FIGURE
6-4: SPI Master-slave Interconnection
©2007 Silicon Storage Technology, Inc.
S71273-03-000
1/07
43
SST [ SILICON STORAGE TECHNOLOGY, INC ]
