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SST39VF800A-70-4I-EKE 参数 Datasheet PDF下载

SST39VF800A-70-4I-EKE图片预览
型号: SST39VF800A-70-4I-EKE
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位/ 4兆位/ 8兆位( X16 )多用途闪存 [2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 31 页 / 845 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash  
SST39LF200A / SST39LF400A / SST39LF800A  
SST39VF200A / SST39VF400A / SST39VF800A  
Data Sheet  
The actual completion of the nonvolatile write is asynchro-  
Data Protection  
nous with the system; therefore, either a Data# Polling or  
Toggle Bit read may be simultaneous with the completion  
of the write cycle. If this occurs, the system may possibly  
get an erroneous result, i.e., valid data may appear to con-  
flict with either DQ7 or DQ6. In order to prevent spurious  
rejection, if an erroneous result occurs, the software routine  
should include a loop to read the accessed location an  
additional two (2) times. If both reads are valid, then the  
device has completed the write cycle, otherwise the rejec-  
tion is valid.  
The SST39LF200A/400A/800A and SST39VF200A/400A/  
800A provide both hardware and software features to pro-  
tect nonvolatile data from inadvertent writes.  
Hardware Data Protection  
Noise/Glitch Protection: A WE# or CE# pulse of less than 5  
ns will not initiate a write cycle.  
VDD Power Up/Down Detection: The Write operation is  
inhibited when VDD is less than 1.5V.  
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#  
high will inhibit the Write operation. This prevents inadvert-  
ent writes during power-up or power-down.  
Data# Polling (DQ7)  
When the SST39LF200A/400A/800A and SST39VF200A/  
400A/800A are in the internal Program operation, any  
attempt to read DQ7 will produce the complement of the  
true data. Once the Program operation is completed, DQ7  
will produce true data. Note that even though DQ7 may  
have valid data immediately following the completion of an  
internal Write operation, the remaining data outputs may  
still be invalid: valid data on the entire data bus will appear  
in subsequent successive Read cycles after an interval of  
1 µs. During internal Erase operation, any attempt to read  
DQ7 will produce a ‘0’. Once the internal Erase operation  
is completed, DQ7 will produce a ‘1’. The Data# Polling is  
valid after the rising edge of fourth WE# (or CE#) pulse for  
Program operation. For Sector-, Block- or Chip-Erase, the  
Data# Polling is valid after the rising edge of sixth WE# (or  
CE#) pulse. See Figure 8 for Data# Polling timing diagram  
and Figure 19 for a flowchart.  
Software Data Protection (SDP)  
The SST39LF200A/400A/800A and SST39VF200A/400A/  
800A provide the JEDEC approved Software Data Protec-  
tion scheme for all data alteration operations, i.e., Program  
and Erase. Any Program operation requires the inclusion of  
the three-byte sequence. The three-byte load sequence is  
used to initiate the Program operation, providing optimal  
protection from inadvertent Write operations, e.g., during  
the system power-up or power-down. Any Erase operation  
requires the inclusion of six-byte sequence. This group of  
devices are shipped with the Software Data Protection per-  
manently enabled. See Table 4 for the specific software  
command codes. During SDP command sequence, invalid  
commands will abort the device to Read mode within TRC.  
The contents of DQ15-DQ8 can be VIL or VIH, but no other  
value, during any SDP command sequence.  
Toggle Bit (DQ6)  
During the internal Program or Erase operation, any con-  
secutive attempts to read DQ6 will produce alternating 1s  
and 0s, i.e., toggling between 1 and 0. When the internal  
Program or Erase operation is completed, the DQ6 bit will  
stop toggling. The device is then ready for the next opera-  
tion. The Toggle Bit is valid after the rising edge of fourth  
WE# (or CE#) pulse for Program operation. For Sector-,  
Block- or Chip-Erase, the Toggle Bit is valid after the rising  
edge of sixth WE# (or CE#) pulse. See Figure 9 for Toggle  
Bit timing diagram and Figure 19 for a flowchart.  
Common Flash Memory Interface (CFI)  
The SST39LF200A/400A/800A and SST39VF200A/400A/  
800A also contain the CFI information to describe the char-  
acteristics of the device. In order to enter the CFI Query  
mode, the system must write three-byte sequence, same  
as Software ID Entry command with 98H (CFI Query com-  
mand) to address 5555H in the last byte sequence. Once  
the device enters the CFI Query mode, the system can  
read CFI data at the addresses given in Tables 5 through 9.  
The system must write the CFI Exit command to return to  
Read mode from the CFI Query mode.  
©2007 Silicon Storage Technology, Inc.  
S71117-09-000  
2/07  
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