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SST39LF200A-45-4C-EK 参数 Datasheet PDF下载

SST39LF200A-45-4C-EK图片预览
型号: SST39LF200A-45-4C-EK
PDF下载: 下载PDF文件 查看货源
内容描述: 2兆位/ 4兆位/ 8兆位( X16 )多用途闪存 [2 Mbit / 4 Mbit / 8 Mbit (x16) Multi-Purpose Flash]
分类和应用: 闪存内存集成电路光电二极管
文件页数/大小: 30 页 / 339 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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2 Mbit / 4 Mbit / 8 Mbit Multi-Purpose Flash  
SST39LF200A / SST39LF400A / SST39LF800A  
SST39VF200A / SST39VF400A / SST39VF800A  
Data Sheet  
ADDRESS A  
MS-0  
T
CE  
CE#  
OE#  
WE#  
T
OES  
T
T
OE  
OEH  
DQ  
6
TWO READ CYCLES  
WITH SAME OUTPUTS  
360 ILL F07.3  
Note:  
A
A
= Most significant address  
MS  
MS  
= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A  
16 17 18  
FIGURE 7: TOGGLE BIT TIMING DIAGRAM  
T
SCE  
SIX-BYTE CODE FOR CHIP-ERASE  
5555 5555 2AAA  
5555  
2AAA  
5555  
ADDRESS A  
MS-0  
CE#  
OE#  
WE#  
T
WP  
DQ  
15-0  
XXAA  
SW0  
XX55  
SW1  
XX80  
SW2  
XXAA  
SW3  
XX55  
SW4  
XX10  
SW5  
360 ILL F08.7  
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are  
interchageable as long as minimum timings are met. (See Table 16)  
A
A
= Most significant address  
MS  
MS  
= A for SST39LF/VF200A, A for SST39LF/VF400A and A for SST39LF/VF800A  
16  
17  
18  
X can be V or V , but no other value.  
IL IH  
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM  
©2001 Silicon Storage Technology, Inc.  
S71117-04-000 6/01 360  
17  
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