16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Ready/Busy# (RY/BY#)
Toggle Bits (DQ6 and DQ2)
The devices include a Ready/Busy# (RY/BY#) output sig-
nal. RY/BY# is an open drain output pin that indicates
whether an Erase or Program operation is in progress.
Since RY/BY# is an open drain output, it allows several
devices to be tied in parallel to VDD via an external pull-up
resistor. After the rising edge of the final WE# pulse in the
command sequence, the RY/BY# status is valid.
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or CE#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the
rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ6 will
toggle.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
Byte/Word (BYTE#)
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ2)
is valid after the rising edge of the last WE# (or CE#) pulse
of a Write operation. See Figure 11 for Toggle Bit timing
diagram and Figure 24 for a flowchart.
The device includes a BYTE# pin to control whether the
device data I/O pins operate x8 or x16. If the BYTE# pin is
at logic “1” (VIH) the device is in x16 data configuration: all
data I/0 pins DQ0-DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is at logic “0”, the device is in x8 data con-
figuration: only data I/O pins DQ0-DQ7 are active and con-
trolled by CE# and OE#. The remaining data pins DQ8-
DQ14 are at Hi-Z, while pin DQ15 is used as the address
input A-1 for the Least Significant Bit of the address bus.
TABLE 1: WRITE OPERATION STATUS
Status
DQ7
DQ6
DQ2
RY/BY#
Normal
Standard
DQ7# Toggle No Toggle
0
Operation Program
Standard
Erase
0
1
Toggle
1
Toggle
Toggle
0
1
Data# Polling (DQ7)
When the devices are in an internal Program operation, any
attempt to read DQ7 will produce the complement of the
true data. Once the Program operation is completed, DQ7
will produce true data. During internal Erase operation, any
attempt to read DQ7 will produce a ‘0’. Once the internal
Erase operation is completed, DQ7 will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 10 for Data# Poll-
ing (DQ7) timing diagram and Figure 24 for a flowchart.
Erase-
Suspend Erase
Mode Suspended
Read From
Sector/Block
Read From
Non-Erase
Suspended
Sector/Block
Data
Data
Data
N/A
1
Program
DQ7# Toggle
0
T1.1 1274
Note: DQ7, DQ6, and DQ2 require a valid address when reading
status information. The address must be in the bank where
the operation is in progress in order to read the operation sta-
tus. If the address is pointing to a different bank (not busy),
the device will output array data.
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
4
SST [ SILICON STORAGE TECHNOLOGY, INC ]
