512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
SST27SF020 SST27SF010
SST27SF010 SST27SF020
SST27SF512
SST27SF512
V
V
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
V
DD
PP
PP
DD
A16
A15
A12
A7
A16
A15
A12
A7
2
PGM#
NC
PGM#
A17
A14
A13
A8
A15
A12
A7
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
3
2
A14
A13
A8
4
A14
A13
A8
3
5
A6
4
32-pin
PDIP
A6
A6
6
A5
5
A9
28-pin
PDIP
A5
A5
7
A9
A9
A4
6
A11
OE#/V
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A4
A4
8
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
A3
7
Top View
PP
A3
A3
9
A2
8
Top View
A2
A2
10
11
12
13
14
15
16
A1
9
A1
A1
A0
10
11
12
13
14
A0
A0
DQ0
DQ1
DQ2
DQ0
DQ1
DQ2
DQ0
DQ1
DQ2
V
SS
V
V
SS
SS
1152 28-pdip P3.2
1152 32-pdip P4.1
FIGURE 3: PIN ASSIGNMENTS FOR 28-PIN AND 32-PIN PDIP
TABLE 2: PIN DESCRIPTION
Symbol
AMS1-A0
DQ7-DQ0
Pin Name
Functions
Address Inputs
Data Input/output
To provide memory addresses
To output data during Read cycles and receive input data during Program cycles
The outputs are in tri-state when OE# or CE# is high.
CE#
Chip Enable
To activate the device when CE# is low
OE#
Output Enable
For SST27SF010/020, to gate the data output buffers during Read operation
OE#/VPP
Output Enable/VPP For SST27SF512, to gate the data output buffers during Read operation and high voltage
pin during Chip-Erase and programming operation
VPP
Power Supply for
Program or Erase
For SST27SF010/020, high voltage pin during Chip-Erase and programming operation
11.4-12V
VDD
VSS
NC
Power Supply
Ground
To provide 5.0V supply (4.5-5.5V)
No Connection
Unconnected pins.
T2.4 1152
1. AMS = Most significant address
A
MS = A15 for SST27SF512, A16 for SST27SF010, and A17 for SST27SF020
©2005 Silicon Storage Technology, Inc.
S71152-11-000
9/05
5
SST [ SILICON STORAGE TECHNOLOGY, INC ]
