512 Kbit / 1 Mbit / 2 Mbit Many-Time Programmable Flash
SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
SST27SF020 SST27SF010
SST27SF512
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SST27SF512
VDD
A14
A13
A8
A9
A11
OE#/VPP
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
1152 28-pdip P3.2
SST27SF010 SST27SF020
1
2
3
4
5
32-pin
6
PDIP
7
8
Top View
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
PGM#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
PGM#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
28-pin
PDIP
Top View
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1152 32-pdip P4.1
FIGURE 3: P
IN
A
SSIGNMENTS FOR
28-
PIN AND
32-
PIN
PDIP
TABLE 2: P
IN
D
ESCRIPTION
Symbol
A
MS1
-A
0
DQ
7
-DQ
0
CE#
OE#
OE#/V
PP
V
PP
V
DD
V
SS
NC
Pin Name
Address Inputs
Data Input/output
Chip Enable
Output Enable
Output Enable/V
PP
Power Supply for
Program or Erase
Power Supply
Ground
No Connection
Unconnected pins.
T2.4 1152
Functions
To provide memory addresses
To output data during Read cycles and receive input data during Program cycles
The outputs are in tri-state when OE# or CE# is high.
To activate the device when CE# is low
For SST27SF010/020, to gate the data output buffers during Read operation
For SST27SF512, to gate the data output buffers during Read operation and high voltage
pin during Chip-Erase and programming operation
For SST27SF010/020, high voltage pin during Chip-Erase and programming operation
11.4-12V
To provide 5.0V supply (4.5-5.5V)
1. A
MS
= Most significant address
A
MS
= A
15
for SST27SF512, A
16
for SST27SF010, and A
17
for SST27SF020
©2005 Silicon Storage Technology, Inc.
S71152-11-000
9/05
5
SST [ SILICON STORAGE TECHNOLOGY, INC ]
