Serial Quad I/O (SQI) Flash Memory
SST26VF016 / SST26VF032
Data Sheet
Read Block-Protection Register (RBPR)
The Read Block-Protection Register instruction outputs the Block-Protection Register data which
determines the protection status. To execute a Read Block-Protection Register operation, the host
drives CE# low, and then sends the Read Block-Protection Register command cycle (72H). Each cycle
is two nibbles long, most significant nibble first.
After the command cycle, the device outputs data on the falling edge of the SCK signal starting with
the most significant nibble, see Tables 8 - 9 for definitions of each bit in the Block-Protection Register.
The RBPR command does not wrap around. After all data has been output, the device will output 0H
until terminated by a low-to-high transition on CE#. See Figure 22.
CE#
MODE 3
0
2
4
6
8
10
12
N
SCK
SIO(3:0)
C1 C0 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5
HN L
MSN LSN
BPR [m:m-7]
BPR [7:0]
1359 F34.2
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble
Block Protection Register (BPR) m = 47/79 for SST26VF016/SST26VF032 respectively
C[1:0]=72H
Figure 22:Read Block Protection Register Sequence
Write Block-Protection Register (WBPR)
To execute a Write Block-Protection Register operation the host drives CE# low; sends the Write
Block-Protection Register command cycle (42H); then sends six cycles of data for SST25VF016, or 10
cycles of data for SST25VF032, and finally drives CE# high. Each cycle is two nibbles long, most sig-
nificant nibble first. See Tables 8 - 9 for definitions of each bit in the Block-Protection Register.
CE#
MODE 3
MODE 0
0
2
4
6
8
10
12
N
SCK
SIO(3:0)
C1 C0 H0 L0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5
HN LN
MSN LSN
BPR [m:m-7]
BPR [7:0]
1359 F35.1
Note: MSN = Most Significant Nibble, LSN = Least Significant Nibble
Block Protection Register (BPR) m = 48/80 for SST26VF016/SST26VF032 respectively
C[1:0]=42H
Figure 23:Write Block Protection Register Sequence
©2010 Silicon Storage Technology, Inc.
S71359-05-000
06/10
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