1.8V Serial Quad I/O (SQI) Flash Memory
SST26WF032
Advance Information
Pin Description
1
2
3
4
8
7
6
5
CE#
V
DD
1
2
3
4
8
7
6
5
CE#
SO/SIO1
SIO2
V
DD
SO/SIO1
SIO2
SIO3
SIO3
Top View
Top View
SCK
SCK
V
SI/SIO0
SS
V
SI/SIO0
SS
1409 08-soic S2A P1.0
1409 08-wson QA P1.0
8-Contact WSON
8-Lead SOIC
Figure 2: Pin Description for 8-lead SOIC and 8-contact WSON
Table 1: Pin Description
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the
clock input, while output data is shifted out on the falling edge of the clock
input.
SIO[3:0]
SI
Serial Data
Input/Output
To transfer commands, addresses, or data serially into the device or data out
of the device. Inputs are latched on the rising edge of the serial clock. Data is
shifted out on the falling edge of the serial clock. The EQIO command
instruction configures these pins for Quad I/O mode.
Serial Data Input To transfer commands, addresses or data serially into the device. Inputs are
for SPI mode
latched on the rising edge of the serial clock. SI is the default state after a
power on reset.
SO
Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling
for SPI mode
edge of the serial clock. SO is the default state after a power on reset.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain
low for the duration of any command sequence; or in the case of Write oper-
ations, for the command/data input sequence.
VDD
VSS
Power Supply
Ground
To provide power supply voltage: 1.65-1.95V
T1.0 1409
©2010 Silicon Storage Technology, Inc.
S71409-01-000
01/10
4
SST [ SILICON STORAGE TECHNOLOGY, INC ]
