8Mbit 1.8V SPI Serial Flash
SST25WF080
Advance Information
PIN DESCRIPTION
Top View
CE#
SO
WP#
V
SS
1
2
3
4
8
7
6
5
V
DD
RST#/HOLD#
SCK
SI
1203.25WF 08-soic-P0.0
FIGURE 2: Pin Assignment for 8-Lead SOIC
Top View
(Balls Facing Down)
2
SI
SCK
RST#/
HOLD#
V
DD
CE#
1
V
SS
WP#
SO
A
B
C
D
1328.25WF 8-xfbga P1.0
FIGURE 3: Pin Assignment for 8-bump XFBGA
TABLE 1: Pin Description
Symbol
SCK
Pin Name
Serial Clock
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin. See
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To reset the operation of the device and the internal logic. The device powers on with
RST# pin functionality as default.
To temporarily stop serial communication with SPI Flash memory while device is
selected. This is selected by an instruction sequence; see “Reset/Hold Mode” on page 5.
To provide power supply voltage: 1.65-1.95V for SST25WF080
T1.0 1203
SI
SO
Serial Data Input
Serial Data Output
CE#
WP#
RST#/HOLD#
Chip Enable
Write Protect
Reset
Hold
V
DD
V
SS
Power Supply
Ground
©2010 Silicon Storage Technology, Inc.
S71203-03-000
04/10
3
SST [ SILICON STORAGE TECHNOLOGY, INC ]
