8Mbit 1.8V SPI Serial Flash
SST25WF080
Advance Information
Hardware End-of-Write Detection
Auto Address Increment (AAI) Word-Program
The Hardware End-of-Write detection method eliminates
the overhead of polling the Busy bit in the Software Status
Register during an AAI Word program operation. The 8-bit
command, 70H, configures the Serial Output (SO) pin to
indicate Flash Busy status during AAI Word programming,
as shown in Figure 10. The 8-bit command, 70H, must be
executed prior to executing an AAI Word-Program instruc-
tion. Once an internal programming operation begins,
asserting CE# will immediately drive the status of the inter-
nal flash status on the SO pin. A ‘0’ indicates the device is
busy and a ‘1’ indicates the device is ready for the next
instruction. De-asserting CE# will return the SO pin to tri-
state.
The AAI program instruction allows multiple bytes of data to
be programmed without re-issuing the next sequential
address location. This feature decreases total program-
ming time when multiple bytes or the entire memory array
is to be programmed. An AAI Word program instruction
pointing to a protected memory area will be ignored. The
selected address range must be in the erased state (FFH)
when initiating an AAI Word Program operation. While
within AAI Word Programming sequence, the only valid
instructions are AAI Word (ADH), RDSR (05H), or WRDI
(04H). Users have three options to determine the comple-
tion of each AAI Word program cycle: hardware detection
by reading the Serial Output, software detection by polling
the BUSY bit in the software status register or wait TBP.
Refer to End-Of-Write Detection section for details.
The 8-bit command, 80H, disables the Serial Output (SO)
pin to output busy status during AAI-Word-program opera-
tion, and re-configures SO as an output pin. In this state,
the SO pin will function as a normal Serial Output pin. At
this time, the RDSR command can poll the status of the
Software Status Register. This is shown in Figure 11.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. The AAI Word Program
instruction is initiated by executing an 8-bit command,
ADH, followed by address bits [A23-A0]. Following the
addresses, two bytes of data are input sequentially, each
one from MSB (Bit 7) to LSB (Bit 0). The first byte of data
(D0) will be programmed into the initial address [A23-A1]
with A0 = 0, the second byte of Data (D1) will be pro-
grammed into the initial address [A23-A1] with A0 = 1. CE#
must be driven high before the AAI Word Program instruc-
tion is executed. The user must check the BUSY status
before entering the next valid command. Once the device
indicates it is no longer busy, data for the next two sequen-
tial addresses may be programmed and so on. When the
last desired byte had been entered, check the busy status
using the hardware method or the RDSR instruction and
execute the Write-Disable (WRDI) instruction, 04H, to ter-
minate AAI. Check the busy status after WRDI to deter-
mine if the device is ready for any command. See Figures
12 and 13 for AAI Word programming sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
SCK
MODE 0
SI
70
MSB
SO
HIGH IMPEDANCE
1203 F09.0
FIGURE 10: Enable SO as Hardware RY/BY#
during AAI Programming
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the
device will exit AAI operation and reset the Write-Enable-
Latch bit (WEL = 0) and the AAI bit (AAI = 0).
CE#
MODE 3
0
1
2
3
4
5
6
7
SCK
MODE 0
End-of-Write Detection
80
SI
There are three methods to determine completion of a pro-
gram cycle during AAI Word programming: hardware
detection by reading the Serial Output, software detection
by polling the BUSY bit in the Software Status Register or
wait TBP.
MSB
SO
HIGH IMPEDANCE
1203 F10.0
FIGURE 11: Disable SO as Hardware RY/BY#
during AAI Programming
©2010 Silicon Storage Technology, Inc.
S71203-03-000
04/10
12
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