64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
Hold Operation
The EHLD instruction enables the hold pin functionality of
the RST#/HOLD# pin. Once converted to a hold pin, the
RST#/HOLD# pin functions as a hold pin until the device is
powered off and on. After the power cycle, the pin function-
ality returns as a reset pin (RST#) after the power on.
Similarly, if the rising edge of the HOLD# signal does not
coincide with the SCK active low state, then the device
exits from Hold mode when the SCK next reaches the
active low state. See Figure 5 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be VIL or VIH.
The HOLD# pin is used to pause a serial sequence using
the SPI flash memory, but without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If CE# is driven high during a Hold condition, the device
returns to Standby mode. As long as HOLD# signal is low,
the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
5 for Hold timing.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
SCK
HOLD#
Active
Hold
Active
Hold
Active
1392 F05.0
FIGURE 5: Hold Condition Waveform
Write Protection
Security ID
SST25VF064C provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-down
function of the status register. The Block-Protection bits
(BP3, BP2, BP1, BP0, and BPL) in the status register pro-
vide Write protection to the memory array and the status
register. See Table 5 for the Block-Protection description.
SST25VF064C offers a 256-bit Security ID (Sec ID) fea-
ture. The Security ID space is divided into two parts – one
factory-programmed, 64-bit segment and one user-pro-
grammable 192-bit segment. The factory-programmed
segment is programmed at SST with a unique number and
cannot be changed. The user-programmable segment is
left unprogrammed for the customer to program as desired.
Write Protect Pin (WP#)
Use the Program SID command to program the Security ID
using the address shown in Table 7. Once programmed,
the Security ID can be locked using the Lockout SID com-
mand. This prevents any future write to the Security ID.
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 3). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
The factory-programmed portion of the Security ID can
never be programmed, and none of the Security ID can be
erased.
TABLE 3: Conditions to execute Write-Status-
Register (WRSR) Instruction
WP#
BPL
1
Execute WRSR Instruction
Not Allowed
L
L
0
Allowed
H
X
Allowed
T3.0 1392
©2010 Silicon Storage Technology, Inc.
S71392-04-000
04/10
6
SST [ SILICON STORAGE TECHNOLOGY, INC ]
