64 Mbit SPI Serial Dual I/O Flash
SST25VF064C
Data Sheet
PIN DESCRIPTION
RST#/HOLD#
SCK
SI/SIO
NC
1
2
3
4
CE#
8
7
6
5
V
DD
V
DD
NC
NC
NC
NC
0
SO/SIO
1
RST#/HOLD#
SCK
Top View
Top View
WP#
NC
V
SS
SI/SIO
0
NC
NC
1392 8-WSON P1.0
CE#
SO/SIO
V
SS
WP#
1
CE#
SO
1
2
3
4
V
8
7
6
5
DD
1392 16-SOIC P1.0
RST#/HOLD#
Top View
WP#
SCK
SI
V
SS
1392 8-soic S3A P1.0
FIGURE 2: Pin Assignments for 16-Lead SOIC, 8-Contact WSON, and 8-Lead SOIC
TABLE 1: Pin Description
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
SIO[0:1]
Serial Data Input/
Output for Dual I/O
Mode
To transfer commands, addresses, or data serially into the device, or data out of the
device.
Inputs are latched on the rising edge of the serial clock.
Data is shifted out on the falling edge of the serial clock. These pins are for Dual I/O
mode.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for
the duration of any command sequence.
WP#
Write Protect
Reset
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
RST#/HOLD#
To reset the operation of the device and the internal logic. The device powers on with
RST# pin functionality as default.
Hold
To temporarily stop serial communication with SPI Flash memory while device is
selected. This is selected by an instruction sequence. See “Reset/Hold Mode” page 5
for details.
VDD
VSS
Power Supply
Ground
To provide power supply voltage: 2.7-3.6V
T1.0 1392
©2010 Silicon Storage Technology, Inc.
S71392-04-000
04/10
3
SST [ SILICON STORAGE TECHNOLOGY, INC ]
