1 Mbit SPI Serial Flash
SST25VF010
Data Sheet
Status Register
The software status register provides status on whether the
flash memory array is available for any Read or Write oper-
ation, whether the device is Write enabled, and the state of
the memory Write protection. During an internal Erase or
Program operation, the status register may be read only to
determine the completion of an operation in progress.
status register.
Busy
The Busy bit determines whether there is an internal Erase
or Program operation in progress. A “1” for the Busy bit indi-
cates the device is busy with an operation in progress. A “0”
indicates the device is ready for the next valid operation.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the inter-
nal memory Write Enable Latch. If the Write-Enable-Latch
bit is set to “1”, it indicates the device is Write enabled. If the
bit is set to “0” (reset), it indicates the device is not Write
enabled and does not accept any memory Write (Program/
Erase) commands. The Write-Enable-Latch bit is automati-
cally reset under the following conditions:
•
•
•
•
•
•
•
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming
reached its highest memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Block Protection (BP1, BP0)
The Block-Protection (BP1, BP0) bits define the size of the
memory area, as defined in Table 4, to be software pro-
tected against any memory Write (Program or Erase)
operations. The Write-Status-Register (WRSR) instruction
is used to program the BP1 and BP0 bits as long as WP#
is high or the Block-Protect-Lock (BPL) bit is 0. Chip-Erase
can only be executed if Block-Protection bits are both 0.
After power-up, BP1 and BP0 are set to 1.
Block Protection Lock-Down (BPL)
WP# pin driven low (V
IL
), enables the Block-Protection-
Lock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP1, and BP0 bits. When the
WP# pin is driven high (V
IH
), the BPL bit has no effect and
its value is “Don’t Care”. After power-up, the BPL bit is
reset to 0.
TABLE 4: S
OFTWARE
S
TATUS
R
EGISTER
B
LOCK
P
ROTECTION1
Status
Register Bit
Protection Level
0
1 (1/4 Memory Array)
2 (1/2 Memory Array)
3 (Full Memory Array)
BP1
0
0
1
1
BP0
0
1
0
1
Protected
Memory Area
None
018000H-01FFFFH
010000H-01FFFFH
000000H-01FFFFH
T4.0 1233
1. Default at power-up for BP1 and BP0 is ‘11’.
Auto Address Increment (AAI)
The Auto Address Increment Programming-Status bit pro-
vides status on whether the device is in AAI programming
mode or Byte-Program mode. The default at power up is
Byte-Program mode.
TABLE 5: S
OFTWARE
S
TATUS
R
EGISTER
Bit
0
1
2
3
4:5
6
Name
BUSY
WEL
BP0
BP1
RES
AAI
Function
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
Indicate current level of block write protection (See Table 4)
Indicate current level of block write protection (See Table 4)
Reserved for future use
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
1 = BP1, BP0 are read-only bits
0 = BP1, BP0 are read/writable
Default at Power-up
0
0
1
1
0
0
Read/Write
R
R
R/W
R/W
N/A
R
7
BPL
0
R/W
T5.0 1233
©2003 Silicon Storage Technology, Inc.
S71233-01-000
8/03
6
SST [ SILICON STORAGE TECHNOLOGY, INC ]
