8Mbit 1.8V SPI Serial Flash
SST25WF080
Advance Information
Reset/Hold Mode
The RST#/HOLD# pin provides either a hardware reset or
a hold pin. From power-on, the RST#/HOLD# pin defaults
as a hardware reset pin (RST#). The Hold mode for this pin
is a user selected option where an Enable-Hold instruction
enables the Hold mode. Once selected as a hold pin
(HOLD#), the RST#/HOLD# pin will be configured as a
HOLD# pin, and goes back to RST# pin only after a power-
off and power-on sequence.
mode. The RST# pin must be driven low for a minimum of
TRST time to reset the device. The SO pin is in high imped-
ance state while the device is in reset. A successful reset will
reset the status register to its power-up state. See Table 4
for default power-up modes. A device reset during an active
Program or Erase operation aborts the operation and data
of the targeted address range may be corrupted or lost due
to the aborted erase or program operation. The device exits
AAI Programming Mode in progress and places the SO pin
in high impedance state.
Reset
If the RST#/HOLD# pin is used as a reset pin, RST# pin
provides a hardware method for resetting the device. Driving
the RST# pin high puts the device in normal operating
CE#
T
T
T
RECR
RECP
RECE
SCK
T
RST
RST#
T
RHZ
SO
SI
1203 F04.0
FIGURE 5: Reset Timing Diagram
TABLE 2: Reset Timing Parameters
Symbol
Parameter
Min
100
Max
Units
1
TRST
Reset Pulse Width
ns
ns
ns
µs
ms
TRHZ
Reset to High-Z Output
Reset Recovery from Read
Reset Recovery from Program
Reset Recovery from Erase
107
100
10
TRECR
TRECP
TRECE
1
T2.1203
1. For reset while in a Programming or Erase mode, the reset pulse must be >5µs
©2010 Silicon Storage Technology, Inc.
S71203-03-000
04/10
5
SST [ SILICON STORAGE TECHNOLOGY, INC ]
