2 Mbit / 4 Mbit SPI Serial Flash
SST25VF020 / SST25VF040
Data Sheet
Read
The Read instruction outputs the data starting from the
specified address location. The data output stream is con-
tinuous through all addresses until terminated by a low to
high transition on CE#. The internal address pointer will
automatically increment until the highest memory address
is reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space, i.e. for
4 Mbit density, once the data from address location
7FFFFH had been read, the next output will be from
address location 00000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits [A23-A0]. CE# must
remain active low for the duration of the Read cycle. See
Figure 4 for the Read sequence.
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
39
40
47 48
55 56
63 64
70
24
32
MODE 0
SCK
03
ADD.
MSB
HIGH IMPEDANCE
ADD.
ADD.
SI
MSB
N
OUT
N+1
N+2
N+3
N+4
D
OUT
D
D
D
D
OUT
OUT
OUT
SO
MSB
1231 F04.1
FIGURE 4: READ SEQUENCE
Byte-Program
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. A Byte-Program instruction applied to a pro-
tected memory area will be ignored.
Program instruction is initiated by executing an 8-bit com-
mand, 02H, followed by address bits [A23-A0]. Following the
address, the data is input in order from MSB (bit 7) to LSB
(bit 0). CE# must be driven high before the instruction is
executed. The user may poll the Busy bit in the software
status register or wait TBP for the completion of the internal
self-timed Byte-Program operation. See Figure 5 for the
Byte-Program sequence.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active low
for the duration of the Byte-Program instruction. The Byte-
CE#
MODE 3
0
1
2
3
4
5
6
7
8
15 16
23
31
39
24
32
MODE 0
SCK
02
ADD.
MSB
ADD.
ADD.
D
IN
MSB LSB
SI
MSB
HIGH IMPEDANCE
SO
1231 F05.1
FIGURE 5: BYTE-PROGRAM SEQUENCE
©2004 Silicon Storage Technology, Inc.
S71231-04-000
6/04
9
SST [ SILICON STORAGE TECHNOLOGY, INC ]
