32 Mbit SPI Serial Flash
SST25VF032B
Data Sheet
Read (25 MHz)
The Read instruction, 03H, supports up to 25 MHz Read.
The device outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high tran-
sition on CE#. The internal address pointer will automati-
cally increment until the highest memory address is
reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space. For exam-
ple, once the data from address location 3FFFFFH has
been read, the next output will be from address location
000000H.
The Read instruction is initiated by executing an 8-bit com-
mand, 03H, followed by address bits [A
23
-A
0
]. CE# must
remain active low for the duration of the Read cycle. See
CE#
MODE 3
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47
48
55 56
63 64
70
SCK
MODE 0
SI
MSB
SO
03
ADD.
MSB
HIGH IMPEDANCE
ADD.
ADD.
N
D
OUT
MSB
1327 F06.0
N+1
D
OUT
N+2
D
OUT
N+3
D
OUT
N+4
D
OUT
FIGURE 5: Read Sequence
High-Speed-Read (80 MHz)
The High-Speed-Read instruction supporting up to 80 MHz
Read is initiated by executing an 8-bit command, 0BH, fol-
lowed by address bits [A
23
-A
0
] and a dummy byte. CE#
must remain active low for the duration of the High-Speed-
Read cycle. See Figure 6 for the High-Speed-Read
sequence.
Following a dummy cycle, the High-Speed-Read instruc-
tion outputs the data starting from the specified address
location. The data output stream is continuous through all
addresses until terminated by a low to high transition on
CE#. The internal address pointer will automatically incre-
ment until the highest memory address is reached. Once
the highest memory address is reached, the address
pointer will automatically increment to the beginning (wrap-
around) of the address space. For example, once the data
from address location 3FFFFFH has been read, the next
output will be from address location 000000H.
CE#
MODE 3
SCK
MODE 0
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
78
SI
0B
ADD.
HIGH IMPEDANCE
ADD.
ADD.
X
N
D
OUT
MSB
N+1
D
OUT
N+2
D
OUT
N+3
D
OUT
N+4
D
OUT
1327 F07.1
SO
FIGURE 6: High-Speed-Read Sequence
©2009 Silicon Storage Technology, Inc.
S71327-03-000
05/09
9
SST [ SILICON STORAGE TECHNOLOGY, INC ]
