32 Mbit SPI Serial Flash
SST25VF032B
Data Sheet
PIN DESCRIPTION
CE#
SO
WP#
V
SS
1
2
Top View
3
4
8
7
6
5
V
DD
HOLD#
SCK
SI
CE#
SO
WP#
V
SS
1
8
V
DD
HOLD#
SCK
SI
2
7
Top View
3
6
4
5
1327 8-SOIC P1.0
1327 8-WSON P1.0
Notes:
1. In AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-of-
FIGURE 2: Pin Assignments for 8-Lead SOIC
TABLE 1: Pin Description
Symbol
SCK
Pin Name
Serial Clock
Functions
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin.
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
To temporarily stop serial communication with SPI flash memory without resetting the
device.
To provide power supply voltage: 2.7-3.6V
T1.0 1327
SI
SO
RY/BY#
CE#
WP#
HOLD#
V
DD
V
SS
Serial Data Input
Serial Data Output
Ready / Busy pin
Chip Enable
Write Protect
Hold
Power Supply
Ground
©2009 Silicon Storage Technology, Inc.
S71327-03-000
05/09
3
SST [ SILICON STORAGE TECHNOLOGY, INC ]
