1 Mbit SPI Serial Flash
SST25VF010A
Data Sheet
Instructions
Instructions are used to Read, Write (Erase and Program),
and configure the SST25VF010A. The instruction bus
cycles are 8 bits each for commands (Op Code), data, and
addresses. Prior to executing any Byte-Program, Auto
Address Increment (AAI) programming, Sector-Erase,
Block-Erase, or Chip-Erase instructions, the Write-Enable
(WREN) instruction must be executed first. The complete
list of the instructions is provided in Table 6. All instructions
are synchronized off a high to low transition of CE#. Inputs
will be accepted on the rising edge of SCK starting with the
TABLE 6: D
EVICE
O
PERATION
I
NSTRUCTIONS1
Bus Cycle
2
Cycle Type/Operation
3,4
Read (20 MHz)
High-Speed-Read (33 MHz)
Sector-Erase
5,6
Block-Erase
Chip-Erase
Byte-Program
Auto Address Increment
(AAI) Program
Read-Status-Register
(RDSR)
Enable-Write-Status-Register
(EWSR)
10
Write-Status-Register
(WRSR)
Write-Enable (WREN)
Write-Disable (WRDI)
Read-ID
most significant bit. CE# must be driven low before an
instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read,
Read-ID and Read-Status-Register instructions). Any low
to high transition on CE#, before receiving the last bit of an
instruction bus cycle, will terminate the instruction in
progress and return the device to the standby mode.
Instruction commands (Op Code), addresses, and data are
all input from the most significant bit (MSB) first.
1
S
IN
03H
0BH
20H
52H or
D8H
60H or
C7H
02H
AFH
05H
50H
01H
06H
04H
90H or
ABH
2
S
OUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
3
S
OUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
Hi-Z
Hi-Z
D
OUT
-
Hi-Z
-
-
Hi-Z
4
S
OUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
Hi-Z
Hi-Z
Note
9
-
-
-
-
Hi-Z
ID
5
S
OUT
S
IN
Hi-Z
Hi-Z
Hi-Z
Hi-Z
-
Hi-Z
Hi-Z
Note
-
-
-
-
Hi-Z
X
X
-
-
-
D
IN
D
IN
-
-
-
-
-
X
6
S
IN
X
S
IN
A
23
-A
16
A
23
-A
16
A
23
-A
16
A
23
-A
16
-
A
23
-A
16
A
23
-A
16
X
-
Data
-
-
00H
S
IN
A
15
-A
8
A
15
-A
8
A
15
-A
8
A
15
-A
8
-
A
15
-A
8
A
15
-A
8
-
-
-
-
-
00H
S
IN
A
7
-A
0
A
7
-A
0
A
7
-A
0
A
7
-A
0
-
A
7
-A
0
A
7
-A
0
-
-
-.
-
-
Addr
11
S
OUT
D
OUT
X
-
-
-
Hi-Z
Hi-Z
Note
-
-
-
-
D
OUT12
S
OUT
D
OUT
Hi-Z
Hi-Z
Note
D
OUT12
T6.0 1265
1. A
MS
= Most Significant Address
A
MS
= A
16
for SST25VF010A
Address bits above the most significant bit of each density can be V
IL
or V
IH
2. One bus cycle is eight clock periods.
3. Operation: S
IN
= Serial In, S
OUT
= Serial Out
4. X = Dummy Input Cycles (V
IL
or V
IH
); - = Non-Applicable Cycles (Cycles are not necessary)
5. Sector addresses: use A
MS
-A
12
, remaining addresses can be V
IL
or V
IH
6. Prior to any Byte-Program, AAI-Program, Sector-Erase, Block-Erase, or Chip-Erase operation, the Write-Enable (WREN)
instruction must be executed.
7. Block addresses for: use A
MS
-A
15
, remaining addresses can be V
IL
or V
IH
8. To continue programming to the next sequential address location, enter the 8-bit command, AFH,
followed by the data to be programmed.
9. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
10. The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in con-
junction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction
to make both instructions effective.
11. Manufacturer’s ID is read with A
0
=0, and Device ID is read with A
0
=1. All other address bits are 00H. The Manufacturer’s and
Device ID output stream is continuous until terminated by a low to high transition on CE#
12. Device ID = 49H for SST25VF010A
©2006 Silicon Storage Technology, Inc.
S71265-02-000
1/06
8
SST [ SILICON STORAGE TECHNOLOGY, INC ]
