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SST25VF010A-33-4E-QAE 参数 Datasheet PDF下载

SST25VF010A-33-4E-QAE图片预览
型号: SST25VF010A-33-4E-QAE
PDF下载: 下载PDF文件 查看货源
内容描述: 1兆位的SPI串行闪存 [1 Mbit SPI Serial Flash]
分类和应用: 闪存内存集成电路时钟
文件页数/大小: 25 页 / 293 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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1 Mbit SPI Serial Flash  
SST25VF010A  
Data Sheet  
Sector-Erase  
The Sector-Erase instruction clears all bits in the selected 4  
KByte sector to FFH. A Sector-Erase instruction applied to  
a protected memory area will be ignored. Prior to any Write  
operation, the Write-Enable (WREN) instruction must be  
executed. CE# must remain active low for the duration of  
the any command sequence. The Sector-Erase instruction  
is initiated by executing an 8-bit command, 20H, followed  
by address bits [A23-A0]. Address bits [AMS-A12]  
(AMS = Most Significant address) are used to determine the  
sector address (SAX), remaining address bits can be VIL or  
VIH. CE# must be driven high before the instruction is exe-  
cuted. The user may poll the Busy bit in the software status  
register or wait TSE for the completion of the internal self-  
timed Sector-Erase cycle. See Figure 8 for the Sector-  
Erase sequence.  
CE#  
MODE 3  
0
1
2
3
4
5
6
7
8
15 16  
23  
31  
24  
MODE 0  
SCK  
20  
ADD.  
MSB  
ADD.  
ADD.  
SI  
MSB  
HIGH IMPEDANCE  
SO  
1265 F08.0  
FIGURE 8: SECTOR-ERASE SEQUENCE  
Block-Erase  
The Block-Erase instruction clears all bits in the selected 32  
KByte block to FFH. A Block-Erase instruction applied to a  
protected memory area will be ignored. Prior to any Write  
operation, the Write-Enable (WREN) instruction must be  
executed. CE# must remain active low for the duration of  
any command sequence. The Block-Erase instruction is  
initiated by executing an 8-bit command, 52H or D8H, fol-  
lowed by address bits [A23-A0]. Address bits [AMS-A15]  
(AMS = Most significant address) are used to determine  
block address (BAX), remaining address bits can be VIL or  
VIH. CE# must be driven high before the instruction is exe-  
cuted. The user may poll the Busy bit in the software status  
register or wait TBE for the completion of the internal self-  
timed Block-Erase cycle. See Figure 9 for the Block-Erase  
sequence.  
CE#  
MODE 3  
0
1
2
3
4
5
6
7
8
15 16  
23  
31  
24  
MODE 0  
SCK  
52 or D8  
ADD.  
MSB  
ADD.  
ADD.  
SI  
MSB  
HIGH IMPEDANCE  
SO  
1265 F09.0  
FIGURE 9: BLOCK-ERASE SEQUENCE  
©2006 Silicon Storage Technology, Inc.  
S71265-02-000  
1/06  
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