FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
Preliminary Specifications
TABLE 14-3: AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 100 pF
See Figures 14-8 and 14-10
T14-3.0 1255
TABLE 14-4: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
100
100
1
TPU-WRITE
µs
T14-4.0 1255
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter
TABLE 14-5: PIN IMPEDANCE (VDD=3.3V, Ta=25 °C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
Pin Inductance
15 pF
12 pF
20 nH
1
CIN
VIN = 0V
2
LPIN
T14-5.0 1255
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. Refer to PCI spec.
©2004 Silicon Storage Technology, Inc.
S71255-00-000
3/04
69
SST [ SILICON STORAGE TECHNOLOGY, INC ]
