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89E52RD2-40-C-NJE 参数 Datasheet PDF下载

89E52RD2-40-C-NJE图片预览
型号: 89E52RD2-40-C-NJE
PDF下载: 下载PDF文件 查看货源
内容描述: 8位8051 Compatibale单片机(MCU)与嵌入式超快闪记忆 [8 bit 8051-Compatibale Microcontroller (MCU) with Embedded SuperFlash Memory]
分类和应用: 微控制器
文件页数/大小: 91 页 / 969 K
品牌: SST [ SILICON STORAGE TECHNOLOGY, INC ]
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FlashFlex51 MCU  
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2  
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2  
Preliminary Specifications  
13.0 SYSTEM CLOCK AND CLOCK OPTIONS  
More specific information about on-chip oscillator design  
can be found in the FlashFlex51 Oscillator Circuit Design  
Considerations application note.  
13.1 Clock Input Options and Recom-  
mended Capacitor Values for Oscillator  
Shown in Figure 13-1 are the input and output of an inter-  
nal inverting amplifier (XTAL1, XTAL2), which can be con-  
figured for use as an on-chip oscillator.  
13.2 Clock Doubling Option  
By default, the device runs at 12 clocks per machine cycle  
(x1 mode). The device has a clock doubling option to  
speed up to 6 clocks per machine cycle. Please refer to  
Table 13-2 for detail.  
When driving the device from an external clock source,  
XTAL2 should be left disconnected and XTAL1 should be  
driven.  
At start-up, the external oscillator may encounter a higher  
capacitive load at XTAL1 due to interaction between the  
amplifier and its feedback capacitance. However, the  
capacitance will not exceed 15 pF once the external signal  
meets the VIL and VIH specifications.  
Clock double mode can be enabled either via the external  
host mode or the IAP mode. Please refer to Table 4-1 for  
the external host mode enabling command and to Table 4-  
6 and Table 4-7 for the IAP mode enabling commands  
(When set, the EDC# bit in SFST register will indicate 6  
clock mode.).  
Crystal manufacturer, supply voltage, and other factors  
may cause circuit performance to differ from one applica-  
tion to another. C1 and C2 should be adjusted appropri-  
ately for each design. Table 13-1, shows the typical values  
for C1 and C2 vs. crystal type for various frequencies  
The clock double mode is only for doubling the inter-  
nal system clock and the internal flash memory, i.e.  
EA#=1. To access the external memory and the peripheral  
devices, careful consideration must be taken. Also note  
that the crystal output (XTAL2) will not be doubled.  
TABLE 13-1:RECOMMENDED VALUES FOR C1 AND  
C2 BY CRYSTAL TYPE  
Crystal  
Quartz  
C1 = C2  
20-30pF  
40-50pF  
Ceramic  
T13-1.0 1255  
XTAL2  
XTAL1  
C
C
NC  
XTAL2  
XTAL1  
2
External  
Oscillator  
Signal  
1
V
SS  
V
SS  
1255 F32.0  
External Clock Drive  
Using the On-Chip Oscillator  
FIGURE 13-1: OSCILLATOR CHARACTERISTICS  
TABLE 13-2: CLOCK DOUBLING FEATURES  
Device  
Standard Mode (x1)  
Clock Double Mode (x2)  
Clocks per  
Machine Cycle  
Max. External Clock Frequency  
(MHz)  
Clocks per  
Machine Cycle  
Max. External Clock Frequency  
(MHz)  
SST89E5xxRD2  
SST89V5xxRD2  
12  
12  
40  
33  
6
6
20  
16  
T13-2.0 1255  
©2004 Silicon Storage Technology, Inc.  
S71255-00-000  
3/04  
67  
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