FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
Preliminary Specifications
6.2.3 SPI Transfer Formats
SCK Cycle #
(for reference)
1
2
3
4
5
6
7
8
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MSB
6
5
4
3
2
1
LSB
LSB
(from Master)
MISO
(from Slave)
MSB
6
5
4
3
2
1
SS# (to Slave)
1255 F20.0
FIGURE
6-5: SPI TRANSFER FORMAT WITH CPHA = 0
SCK Cycle #
(for reference)
1
2
3
4
5
6
7
8
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MSB
MSB
6
5
4
3
3
2
2
1
1
LSB
LSB
(from Master)
MISO
(from Slave)
6
5
4
SS# (to Slave)
1255 F21.0
FIGURE
6-6: SPI TRANSFER FORMAT WITH CPHA = 1
©2004 Silicon Storage Technology, Inc.
S71255-00-000
3/04
49