FlashFlex51 MCU
SST89E52RD2 / SST89E54RD2 / SST89E58RD2 / SST89E516RD2
SST89V52RD2 / SST89V54RD2 / SST89V58RD2 / SST89V516RD2
Preliminary Specifications
3.5 Dual Data Pointers
The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data
pointers is accessed. When DPS=0, DPTR0 is selected; when DPS=1, DPTR1 is selected. Quickly switching
between the two data pointers can be accomplished by a single INC instruction on AUXR1. (See Figure 3-6)
AUXR1 / bit0
DPS
DPTR1
DPTR0
DPS = 0 → DPTR0
DPL
82H
DPH
83H
DPS = 1 → DPTR1
External Data Memory
1255 F06.0
FIGURE
3-6: DUAL DATA POINTER ORGANIZATION
3.6 Special Function Registers
Most of the unique features of the FlashFlex51 microcontroller family are controlled by bits in special function regis-
ters (SFRs) located in the SFR memory map shown in Table 3-6. Individual descriptions of each SFR are provided
and reset values indicated in Tables 3-7 to 3-11.
TABLE
3-6: FLASHFLEX51 SFR MEMORY MAP
8 BYTES
F8H
F0H
E8H
E0H
D8H
D0H
C8H
C0H
B8H
B0H
A8H
A0H
98H
90H
88H
80H
IP11
B1
IEA1
ACC1
CCON1
PSW1
T2CON1
WDTC1
IP1
P31
IE1
P21
SCON1
P11
CH
CL
CCAP0H
CCAP0L
CCAP1H
CCAP2H
CCAP3H
CCAP3L
CCAP4H
CCAP4L
FFH
F7H
EFH
E7H
DFH
D7H
CFH
C7H
BFH
B7H
AFH
A7H
9FH
97H
8FH
IP1H
CCAP1L
CCAP2L
CMOD
T2MOD
CCAPM0 CCAPM1 CCAPM2 CCAPM3 CCAPM4
SPCR
RCAP2L
RCAP2H
TL2
TH2
SADEN
SFCF
SFCM
SPSR
SFAL
SFAH
SFDT
P4
SFST
IPH
SADDR
XICON
AUXR1
SBUF
TCON1
P01
TMOD
SP
TL0
TL1
TH0
TH1
AUXR
SPDR
DPL
DPH
WDTD
PCON
87H
T3-6.0 1255
1. Bit addressable SFRs
©2004 Silicon Storage Technology, Inc.
S71255-00-000
3/04
17
SST [ SILICON STORAGE TECHNOLOGY, INC ]
