signals between ground traces and cross digital
lines at right angles only.
7) and analog common (pin 9) is sufficient. VEE
isgeneratedinternallysopin11maybegrounded
or connected to a negative supply if the SPx74A
is being used to upgrade an already existing
design.
Grounding Considerations
Any ground path from the analog and digital
ground should be as low resistance as possible to
accommodate the ground currents present with
this device.
CALIBRATION AND CONNECTION
PROCEDURES
Unipolar
Theanaloggroundcurrentisapproximately6mA
DC while the digital ground is 3mA DC. The
analog and digital common pins should be tied
together as close to the package as possible to
guarantee best performance. The code–depen-
dent currents flow through the VLOGIC and V
terminals and not through the analog and digitCaCl
common pins.
The calibration procedure consists of adjusting
the converter’s most negative output to its ideal
value for offset adjustment, and then adjusting
themostpositiveoutputtoitsidealvalueforgain
adjustment.
Starting with offset adjustment and referring to
Figure4,themidpointofthefirstLSBincrement
shouldbepositionedattheorigintogetanoutput
code of all 0s. To do this, an input of +1⁄2 LSB or
+1.22mVforthe10Vrangeand+2.44mVforthe
20V range should be applied to the SPx74A.
Adjust the offset potentiometer R1 for code tran-
sition flickers between 0000 0000 0000 and
0000 0000 0001.
Power Supplies
The supply voltages for the SPx74A must be
kept as quiet as possible from noise pickup and
also regulated from transients or drops. Because
the part has 12–bit accuracy, voltage spikes on
the supply lines can cause several LSB devia-
tions on the output. Switching power supply
noise can be a problem. Careful filtering and
shielding should be employed to prevent the
noise from being picked up by the converter.
The gain adjustment should be done at positive
full scale. The ideal input corresponding to the
last code change is applied. This is 11⁄2LSB
below the nominal full scale which is +9.9963V
for the 10V range and +19.9927V for the 20V
range.AdjustthegainpotentiometerR2 forflicker
between codes 1111 1111 1110 and 1111 1111
1111. If calibration is not necessary for the
intended application, replace R with a 50Ω, 1%
metal film resistor and remove 2the network ana-
Capacitor bypass pairs are needed from each
supply pin to its respective ground to filter noise
and counter the problems caused by the varia-
tions in supply current. A 10µF tantalum and a
0.1µF ceramic type in parallel between VLOGIC
(pin1)anddigitalcommon(pin15), andVCC (pin
NIBBLE B ZERO
OVERRIDE
NIBBLE A, B
INPUT BUFFERS
12/8
NIBBLE C
READ CONTROL
CS
A
0
R/C
CE
Q
D
H
CK
R
EOC8
CK
Q
DELAY
STS
D
Q
A
LATCH
0
EOC12
Figure 6. SPx74A Control Logic
10