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HS574AS/883 参数 Datasheet PDF下载

HS574AS/883图片预览
型号: HS574AS/883
PDF下载: 下载PDF文件 查看货源
内容描述: [ADC, Successive Approximation, 12-Bit, 1 Func, 1 Channel, Parallel, Word Access, CDIP28, 0.600 INCH, CERDIP-28]
分类和应用: 转换器
文件页数/大小: 14 页 / 204 K
品牌: SPECTRUM [ SPECTRUM MICROWAVE, INC. ]
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the LSB at the beginning of the conversion cycle  
toprovideanoutputvoltagefromtheCDACthat  
is equal to the input signal voltage (which is  
divided by the input voltage divider network).  
Thecomparatordetermineswhethertheaddition  
ofeachsuccessively–weightedbitvoltagecauses  
theCDACoutputvoltagesummationtobegreater  
or less than the input voltage; if the sum is less,  
the bit is left on; if more, the bit is turned off.  
After testing all the bits, the SAR contains a 12–  
bit binary code which accurately represents the  
input signal to within ±12 LSB.  
FEATURES…  
The HS574A/SP674A feature standard bipolar  
and unipolar input ranges of 10V and 20V. Input  
ranges are controlled by a bipolar offset pin and  
laser-trimmed for specified linearity, gain and  
offset accuracy. Power requirements are +5V  
and +12V to +15V with a maximum dissipation  
of 150mW at the specified voltages. Conversion  
times of 8µs, 10µs, 15µs and 25µs are available,  
asareunitswith10,25or50ppm/°Ctemperature  
coefficients for flexible matching to specific  
application requirements.  
Theinternalreferenceprovidesthevoltagerefer-  
ence to the CDAC with excellent stability over  
temperature and time. The reference is trimmed  
to 10.00 Volts ±1% and can supply up to 2mA to  
an external load in addition to that required to  
drive the reference input resistor (1mA) and  
offset resistor (1mA) when operating with ±15V  
supplies. If the HS574A/SP674A is used with  
±12V supplies, or if external current must be  
supplied over the full temperature range, an  
external buffer amplifier is recommended. Any  
externalloadonthe HS574A/SP674Areference  
must remain constant during conversion.  
The HS574A/SP674A are available in six prod-  
uct grades for each conversion time. The –J, –K  
and –L models are specified over 0˚C to + 70˚C  
commercial temperature range; the –S, –T and –  
Umodelsarespecifiedoverthe55˚Cto+125˚C  
military temperature range. Processing in accor-  
dance with MIL–STD–883C is also available.  
The HS574A/SP674A are packaged in a 28–pin  
CerDIP. Please consult the factory for other  
packaging options.  
CIRCUIT OPERATION…  
The HS574A/SP674A are complete 12–bit ana-  
log-to-digital converters with integral voltage  
reference, comparator, successive–approxima-  
tion register (SAR), sample–and–hold, clock,  
output buffers and control circuitry. The high  
level of integration of the HS574A/SP674A  
means they require few external components.  
The sample and hold is a default function by  
virtue of the CDAC architecture. Therefore the  
majority of the S/H specifications are included  
within the A/D specifications.  
Sample–and–Hold Function  
Although there is no sample-and-hold circuit in  
the classical sense, the sampling nature of the  
capacitive DAC makes the HS574A/SP674A  
appear to have a built in sample and hold. This  
sample and hold action substantially increases  
the usefulness of the HS574A/SP674Aover that  
of similar competing devices.  
WhenthecontrolsectionoftheHS574A/SP674A  
initiates a conversion command, the clock is  
enabled and the successive–approximation reg-  
ister is reset to all zeros. Once the conversion  
cycle begins, it can not be stopped or re–started  
and data is not available from the output buffers.  
Note that even though the user may use an  
external sample and hold for very high fre-  
quency inputs, the internal sample and hold still  
provides a very useful isolation function. Once  
theinternalsampleistakenbytheCDACcapaci-  
tance, the input of the HS574A/SP674A is dis-  
connected from the input. This prevents tran-  
sients occurring during conversion from being  
inflicted upon the attached buffer. All other 574/  
674circuitswillcauseatransientloadcurrenton  
TheSAR, timedbytheclock, sequencesthrough  
the conversion cycle and returns an end–of–  
convert flag to the control section of the ADC.  
The clock is then disabled by the control section,  
the output status goes low, and the control sec-  
tion is enabled to allow the data to be read by  
external command.  
The internal HS574A/SP674A 12–bit CDAC is  
sequenced by the SAR starting from the MSB to  
7