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SL23EP04 参数 Datasheet PDF下载

SL23EP04图片预览
型号: SL23EP04
PDF下载: 下载PDF文件 查看货源
内容描述: 低抖动和偏斜10到220兆赫零延迟缓冲器( ZDB ) [Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer(ZDB)]
分类和应用:
文件页数/大小: 14 页 / 164 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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Preliminary  
SL23EP04  
Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB)  
Key Features  
Description  
The SL23EP04 is a low skew, low jitter and low power  
Zero Delay Buffer (ZDB) designed to produce up to four  
(4) clock outputs from one (1) reference input clock, for  
high speed clock distribution applications.  
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x
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10 to 220 MHz operating frequency range  
Low output clock skew: 60ps-typ  
Low output clock Jitter:  
- 35 ps-typ at 166MHz, CL=15pF and VDD=3.3V  
- 45 ps-typ at 166MHz, CL=15pF and VDD=2.5V  
Low part-to-part output skew: 150 ps-typ  
3.3V to 2.5V power supply range  
Low power dissipation:  
The product has an on-chip PLL and a feedback pin  
(FBK) which can be used to obtain feedback from any  
one of the 4 output clocks. The SL23EP04 offers X/2,1X  
and 2X frequency options at the output with respect to  
input reference clock. Refer to the “Product Configuration  
Table” for the details of these options.  
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x
- 12 mA-typ at 66MHz and VDD=3.3V  
- 10 mA-typ at 66MHz and VDD=2.5V  
One input drives 4 outputs  
The SL23EP04-1H and -2H High Drive version operates  
up to 220 MHz and 200MHz at 3.3 and 2.5V power  
supplies respectively. The standard versions -1 and -2  
operate up to 167MHz and 135MHz at 3.3V and 2.5V  
power supplies respectively with CL=15pF output load.  
x
x
x
x
x
Multiple configurations and drive options  
SpreadThru™ PLL that allows use of SSCG  
Available in 8-pin SOIC package  
The SL23EP04 enter into Power Down (PD) mode if the  
input at CLKIN is DC (GND to VDD). In this state all 4  
output clocks are tri-stated and the PLL is turned off,  
leading to 8ȝA-typ power supply current draw.  
Available in Commercial and Industrial grades  
Applications  
Benefits  
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x
x
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x
Printers, MFPs and Digital Copiers  
PCs and Work Stations  
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x
Up to four (4) distribution of input clock  
Routers, Switchers and Servers  
Datacom and Telecom  
Standard and High-Drive levels to control  
impedance level, frequency range and EMI  
x
Low skew, jitter and power dissipation  
High-Speed Digital Embeded Systems  
Block Diagram  
Rev 1.1, May 25, 2007  
Page 1 of 14  
2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com