SL23EP04
Input Duty Cycle
DC1
DC2
Measured at VDD/2, all versions
40
45
50
50
60
55
%
CL=15pF, Fout=66 MHz, all versions
Measured at VDD/2
Output Duty Cycle
%
%
CL=15pF, Fout=133 MHz, all versions
Measured at VDD/2
Output Duty Cycle
DC3
DC4
45
40
-
50
50
-
55
60
CL=15pF, Fout=166 MHz, all versions
Measured at VDD/2
Output Duty Cycle
%
CL=30pF, -1 and -2 versions
Measured at 0.6 to 1.8V
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
Output Rise/Fall Time
tr/f1
2.4
1.7
1.7
1.4
175
150
300
ns
ns
ns
ns
ps
ps
ps
CL=15pF, -1 and -2 versions
Measured at 0.6 to 1.8V
tr/f2
-
-
CL=30pF, -1H and -2H versions
Measured at 0.6 to 1.8V
tr/f3
-
-
CL=15pF, -1H and -2H versions
Measured at 0.6 to 1.8V
tr/f4
-
-
Output-to-Output Skew
on Same Bank
-1 and -2, measured at VDD/2
and outputs are equally loaded
SKW1
SKW2
SKW3
-
80
70
125
Output-to-Output Skew
on Same Bank
-1H and -2H, measured at VDD/2
and outputs are equally loaded
-
Output-to-Output Skew
Between Bank A and B
-1 and -2, measured at VDD/2
and outputs are equally loaded
-
Output-to-Output Skew
Between Bank A and B
-1H and -2H, measured at VDD/2
and outputs are equally loaded
SKW4
SKW5
-
-
110
175
250
450
ps
ps
All versions, measured at VDD/2 and
outputs are equally loaded
Device-to-Device Skew
Input-to-Output Delay
All versions, CLKIN to FBK rising
edge, measured at VDD/2 and outputs
are equally loaded
Dt
-250
+/-90
250
ps
Fout=66.6 MHz and CL=15pF
Fout=133.3 MHz and CL=15pF
-
-
70
60
140
120
ps
ps
Cycle-to-Cycle Jitter
(-1 and -2 Versions)
CCJ1
Switching Electrical Characteristics (C-Grade and VDD=2.5V)
Unless otherwise stated VDD= 2.5+/- 10%, CL=15pF and Ambient Temperature range 0 to +70°C
Fout=66.6 MHz and CL=15pF
Fout=166.6 MHz and CL=15pF
-
-
60
50
120
100
ps
ps
Cycle-to-Cycle Jitter
CCJ2
(-1H and -2H Versions)
From 0.95VDD and valid clock
presented at CLKIN
PLL Lock Time
tLOCK
-
-
1.0
ms
Rev 1.1, May 25, 2007
Page 9 of 14
SPECTRALINEAR [ SPECTRALINEAR INC ]
