SL2309
S2
S1
Clock A1-A4
Clock B1-4
CLKOUT
Output Source
PLL Status
0
0
Tri-state
Tri-state
Driven
PLL
On
On
Off
On
0
1
1
1
0
1
Driven
Driven
Driven
Tri-state
Driven
Driven
Driven
Driven
Driven
PLL
Reference
PLL
Table 2. Select Input Decoding
1500
1000
500
0
-30
-25
-15
-10
-5
0
5
10
15
20
25
30
-20
-500
-1000
-1500
Output Load Difference: FBK Load – CLKA or CLKB Load (pF)
Figure 1. CLKIN Input to CLK A and B Delay
(In terms of load difference between CLKOUT and CLK A and B)
Rev 1.1, May 29, 2007
Page 4 of 12