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SL2309SC-1HT 参数 Datasheet PDF下载

SL2309SC-1HT图片预览
型号: SL2309SC-1HT
PDF下载: 下载PDF文件 查看货源
内容描述: 低抖动和偏斜10到140MHz的零延迟缓冲器( ZDB ) [Low Jitter and Skew 10 to 140MHz Zero Delay Buffer (ZDB)]
分类和应用:
文件页数/大小: 12 页 / 143 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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SL2309  

Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB)  
Key Features  
Description  
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x
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10 to 140 MHz operating frequency range  
Low output clock skew: 50ps-typ  
Low output clock jitter:  
The SL2309 is a low skew, low jitter and low power Zero  
Delay Buffer (ZDB) designed to produce up to nine (9)  
clock outputs from one (1) reference input clock, for high  
speed clock distribution applications.  

50 ps-typ cycle-to-cycle jitter  
The product has an on-chip PLL which locks to the input  
clock at CLKIN and receives its feedback internally from  
the CLKOUT pin.  
x
x
x
Low part-to-part output skew: 150 ps-typ  
3.3 V power supply range  
Low power dissipation:  
The SL2309 has two (2) clock driver banks each with four  
(4) clock outputs. These outputs are controlled by two (2)  
select input pins S1 and S2. When only four (4) outputs  
are needed, four (4) bank-B output clock buffers can be tri-  
stated to reduce power dissipation and jitter. The select  
inputs can also be used to tri-state both banks A and B or  
drive them directly from the input bypassing the PLL and  
making the product behave like a Non-Zero Delay Buffer  
(NZDB).  


28 mA-max at 66 MHz  
44 mA –max at 140 MHz  
x
x
x
x
x
x
One input drives 9 outputs organized as 4+4+1  
Select mode to bypass PLL or tri-state outputs  
SpreadThru™ PLL that allows use of SSCG  
Standard and High-Drive options  
Available in 16-pin SOIC and TSSOP packages  
Available in Commercial and Industrial grades  
The high-drive (-1H) version operates up to 140MHz and  
low drive (-1) version operates up to 100MHz at 3.3V.  
Applications  
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x
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x
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Printers and MFPs  
Benefits  
Digital Copiers  
x
x
Up to nine (9) distribution of input clock  
PCs and Work Stations  
DTV  
Standard and High-Dirive levels to control impedance  
level, frequency range and EMI  
Routers, Switchers and Servers  
Digital Embeded Systems  
x
x
Low power dissipation, jitter and skew  
Low cost  
Block Diagram  
Low Power and  
Low Jitter  
PLL  
MUX  
CLKOUT  
CLKIN  
CLKA1  
CLKA2  
CLKA3  
CLKA4  
S2  
S1  
Input Selection  
Decoding Logic  
CLKB1  
CLKB2  
CLKB3  
CLKB4  
2
2
VDD  
GND  
Rev 1.1, May 29, 2007  
Page 1 of 12  
2200 Laurelwood Road, Santa Clara, CA 95054 Tel: (408) 855-0555 Fax: (408) 855-0550 www.SpectraLinear.com