CY28RS400
1.8mS
CPU_STOP#
PD
CPUT(Free Running
CPUC(Free Running
CPUT(Stoppable)
CPUC(Stoppable)
Figure 7. CPU_STP#= Driven, CPU_PD = Driven
1.8mS
CPU_STOP#
PD
CPUT(Free Running)
CPUC(Free Running)
CPUT(Stoppable)
CPUC(Stoppable)
Figure 8. CPU_STP# = Hi-Z, CPU_PD = Hi-Z
CLK_REQ[0:1]# Description
SRC signals is SRCT clock = High and SRCC = Low. There is
to be no change to the output drive current values, SRCT will
be driven high with a current value equal 6 x Iref,. When the
control register CLKREQ# drive mode bit is programmed to
‘1’, the final state of all stopped DIF signals is low, both SRCT
clock and SRCC clock outputs will not be driven.
The CLKREQ#[1:0] signals are active low input used for clean
stopping and starting selected SRC outputs. The outputs
controlled by CLKREQ#[1:0] are determined by the settings in
register bytes 4 and 5. The CLKREQ# signal is a de-bounced
signal in that it’s state must remain unchanged during two
consecutive rising edges of DIFC to be recognized as a valid
assertion or de-assertion. (The assertion and de-assertion of
this signal is absolutely asynchronous).
CLK_REQ[0:1]# Assertion [High to Low transition]
All differential outputs that were stopped are to resume normal
operation in a glitch free manner. The maximum latency from
the assertion to active outputs is between two–six SRC clock
periods (two clocks are shown) with all SRC outputs resuming
CLK_REQ[0:1]# De-assertion [Low to High transition]
The impact of deasserting the CLKREQ#[1:0] pins is all DIF
outputs that are set in the control registers to stoppable via
de-assertion of CLKREQ#[1:0] are to be stopped after their
next transition. When the control register CLKREQ# drive
mode bit is programmed to ‘0’, the final state of all stopped
simultaneously. If the CLKREQ#
drive mode bit is
programmed to ‘1’ (three-state), the all stopped SRC outputs
must be driven high within 10 ns of CLKREQ#[1:0] assertion
to a voltage greater than 200 mV.
CLKREQ#X
SRCT(free running)
SRCC(free running)
SRCT(stoppable)
SRCT(stoppable)
Figure 9. CLK_REQ#[0:1] Assertion/Deassertion Waveform
Rev 1.0,November 22, 2006
Page 11 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
