CY28RS400
Tstable
<1.8nS
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
REF
Tdrive_PWRDN#
<300PS, >200mV
Figure 4. Power-down Deassertion Timing Waveform
CPU_STP# Assertion
CPUT = HIGH and CPUC = LOW. There is no change to the
output drive current values during the stopped state. The
CPUT is driven HIGH with a current value equal to 6 x (Iref),
and the CPUC signal will be Hi-Z. When the control register
CPU_STP Hi-Z bit corresponding to the output of interest is
programmed to ‘1’, the final state of the stopped CPU clock is
low (due to external 50 ohm pull-down resistor), both CPUT
clock and CPUC clock outputs will not be driven.
The CPU_STP# signal is an active low input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped within two–six CPU clock
periods after being sampled by two rising edges of the internal
CPUC clock. The final states of the stopped CPU signals are
CPU_STP#
CPUT
CPUC
Figure 5. CPU_STP# Assertion Waveform
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is 2 - 6 CPU clock cycles.
CPU_STP#
CPUT
CPUC
CPUT Internal
CPUC Internal
Tdrive_CPU_STP#,10nS>200mV
Figure 6. CPU_STP# Deassertion Waveform
Rev 1.0,November 22, 2006
Page 10 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
