CY28419
Test and Measurement Set-up
For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
M e a s u re m e n t
P o in t
T P C B
ꢀ ꢀ :
C P U T
ꢁ ꢂ ꢃꢂ :
2 p F
M e a s u re m e n t
P o in t
2 p F
T P C B
ꢁ ꢂ ꢃꢂ :
ꢀ ꢀ :
C P U C
IR E F
ꢁ ꢄ ꢅ :
Figure 7. 0.7V Load Configuration
O u tp u t u n d e r Te s t
P ro b e
L o a d C a p
3.3V sig n als
tD C
-
-
3 .3 V
2 .0 V
1 .5 V
0 .8 V
0 V
T r
T f
Figure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)
Table 10.CPU Clock Current Select Function
Board Target Trace/Term Z
Reference R, Iref – VDD (3*Rr)
Output Current
Voh @ Z
50 Ohms
RREF = 475 1ꢀ, IREF = 2.32 mA
Ioh = 6*Iref
0.7V @ 50
Ordering Information
Part Number
Package Type
Product Flow
CY28419OC
CY28419OCT
CY28419ZC
CY28419ZCT
56-pin Shrunk Small Outline package (SSOP)
Commercial, 0q to 70qC
Commercial, 0q to 70qC
Commercial, 0q to 70qC
56-pin Shrunk Small Outline package (SSOP) – Tape and Reel
56-pin Thin Shrunk Small Outline package (TSSOP)
56-pin Thin Shrunk Small Outline package (TSSOP) – Tape and Reel Commercial, 0q to 70qC
Rev 1.0,November 22, 2006
Page 14 of 15
SPECTRALINEAR [ SPECTRALINEAR INC ]
