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CY28419OC 参数 Datasheet PDF下载

CY28419OC图片预览
型号: CY28419OC
PDF下载: 下载PDF文件 查看货源
内容描述: 时钟合成器与差分SRC和CPU输出 [Clock Synthesizer with Differential SRC and CPU Outputs]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 15 页 / 208 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28419  
AC Electrical Specifications (continued)  
Parameter  
Description  
Conditions  
Min.  
Max.  
Unit  
PCI / PCIF  
TDC  
PCIF and PCI Duty Cycle  
Measurement at 1.5V  
45  
55  
ns  
ns  
nS  
nS  
nS  
TPERIOD  
TPERIOD  
THIGH  
Spread Disabled PCIF/PCI Period Measurement at 1.5V  
Spread Enabled PCIF/PCI Period Measurement at 1.5V  
29.9910 30.0009  
29.9910 30.1598  
PCIF and PCI High Time  
PCIF and PCI Low Time  
Measurement at 2.0V  
12.0  
12.0  
0.5  
TLOW  
Measurement at 0.8V  
TR / TF  
TSKEW  
PCIF and PCI rise and fall times  
Measured between 0.8V and 2.0V  
Measurement at 1.5V  
2.0  
Any PCI Clock to Any PCI Clock  
Skew  
500  
250  
pS  
ps  
TCCJ  
PCIF and PCI Cycle-to-Cycle Jitter Measurement at 1.5V  
DOT  
TDC  
DOT Duty Cycle  
DOT Period  
Measurement at 1.5V  
Measurement at 1.5V  
Measurement at 2.0V  
Measurement at 0.8V  
Measured between 0.8V and 2.0V  
10-Ps period  
45  
55  
ns  
nS  
nS  
ns  
ns  
TPERIOD  
THIGH  
TLOW  
20.8257 20.8340  
DOT High Time  
DOT Low Time  
Rise and Fall Times  
Long-term Jitter  
8.994  
8.794  
0.5  
10.486  
10.386  
1.0  
TR / TF  
TLTJ  
2.0  
USB  
TDC  
USB Duty Cycle  
USB Period  
Measurement at 1.5V  
Measurement at 1.5V  
Measurement at 2.0V  
Measurement at 0.8V  
Measured between 0.8V and 2.0V  
125-Ps period  
45  
55  
ns  
nS  
nS  
ns  
ns  
TPERIOD  
THIGH  
TLOW  
20.8257 20.8340  
USB High Time  
USB Low Time  
Rise and Fall Times  
Long-term Jitter  
8.094  
7.694  
1.0  
10.036  
9.836  
2.0  
TR / TF  
TLTJ  
6.0  
REF  
TDC  
REF Duty Cycle  
Measurement at 1.5V  
45  
69.827  
1.0  
55  
69.855  
4.0  
ns  
TPERIOD  
TR / TF  
TCCJ  
REF Period  
Measurement at 1.5V  
REF Rise and Fall Times  
REF Cycle-to-Cycle Jitter  
Measured between 0.8V and 2.0V  
Measurement at 1.5V  
V/ns  
ps  
1000  
ENABLE/DISABLE and SET-UP  
TSTABLE Clock Stabilization from Power-up  
TSS  
10.0  
0
1.8  
ms  
ns  
ns  
Stopclock Set-up Time  
Stopclock Hold Time  
TSH  
Table 7. Group Timing Relationship and Tolerances  
Offset  
Table 9. Maximum Lumped Capacitive Output Loads  
Clock  
Max Load  
Unit  
pF  
Group  
Conditions  
Min.  
Max.  
PCI Clocks  
3V66 Clocks  
USB Clock  
DOT Clock  
REF Clock  
30  
30  
20  
10  
30  
3V66 to PCI  
3V66 Leads PCI  
1.5 ns 3.5 ns  
pF  
pF  
Table 8. USB to DOT Phase Offset  
pF  
Parameter  
DOT Skew  
USB Skew  
VCH SKew  
Typical  
0°  
Value  
0.0ns  
0.0ns  
0.0ns  
Tolerance  
1000 ps  
1000 ps  
1000 ps  
pF  
180°  
0°  
Rev 1.0,November 22, 2006  
Page 13 of 15  
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