CY28411
samples the FS_A, FS_B and FS_C input values. For all logic
levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a
Frequency Select Pins (FS_A, FS_B and FS_C)
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C inputs prior to
VTT_PWRGD# assertion (as seen by the clock synthesizer).
Upon VTT_PWRGD# being sampled low by the clock chip
(indicating processor VTT voltage is stable), the clock chip
one-shot functionality in that once
a valid low on
VTT_PWRGD# has been sampled, all further VTT_PWRGD#,
FS_A, FS_B and FS_C transitions will be ignored, except in
test mode.
Table 1. Frequency Select Table FS_A, FS_B and FS_C
FS_C
MID
0
FS_B
FS_A
CPU
SRC
PCIF/PCI
33 MHz
33 MHz
REF0
DOT96
96 MHz
96 MHz
USB
0
0
1
1
0
0
1
1
0
1
1
1
1
1
0
0
0
0
1
x
100 MHz
133 MHz
100 MHz
100 MHz
14.318 MHz
14.318 MHz
48 MHz
48 MHz
0
0
0
MID
MID
MID
1
RESERVED
Hi-Z
Hi-Z
Hi-Z
Hi-Z
REF
REF
Hi-Z
REF
REF
Hi-Z
REF
REF
1
0
1
REF/2
REF/2
REF/8
REF/8
REF/24
REF/24
1
Serial Data Interface
Data Protocol
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 2.
The block write and block read protocol is outlined in Table 3
while Table 4 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 2. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 3. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address – 7 bits
Write
8:2
9
Slave address – 7 bits
Write
10
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
10
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
18:11
19
18:11
19
27:20
Byte Count – 8 bits
(Skip this step if I2C_EN bit set)
20
Rev 1.0,November 22, 2006
Page 3 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
