CY28354-400
Layout Example for DDR 2.5V
FB
10 mF
VDDQ2
0.005 mF
C3
G
G
C4
V
G
V
G
48
47
46
45
1
2
3
4
G
G
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
5
6
7
8
9
10
G
G
V
G
V
G
G
G
11
12
13
14
15
16
17
18
19
20
21
22
23
24
G
G
V
G
V
G
G
G
V
G
28
27
26
25
G
G
V
G
G
G
FB = Dale ILB1206 - 300 (300:ꢀ@ 100 MHz) or TDK ACB 2012L-120
PF PF
Ceramic Caps C3 = 10–22
C4 = 0.005
= VIA to GND plane layer
V =VIA to respective supply plane layer
G
Note: Each supply plane or strip should have a ferrite bead and capacitors
All bypass caps = 0.1ꢀPF ceramic
Ordering Information
Ordering Code
Package Type
Operating Range
Lead Free
CY28354OXC–400
CY28354OXC–400T
48-pin SSOP
48-pin SSOP – Tape and Reel
Commercial, 0°C to 85 °C
Commercial, 0°C to 85 °C
Rev 1.0,November 22, 2006
Page 7 of 8
SPECTRALINEAR [ SPECTRALINEAR INC ]
