CY28347
Table 8. Dial-A-Ratio™ AGP(0:2)
DARAG (1:0)
CU/AGP Ratio
00
01
10
11
Frequency Selection Default
2/1
2.5/1
3/1
Byte 5: DDR Clock Register
Bit
7
@Pup
Pin#
45
Name
Description
0
1
BUF_IN threshold voltage DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05V.
6
46
FBOUT
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
5
4
3
2
1
0
1
1
1
1
1
1
29,30
31,32
35,36
37,38
41,42
43,44
DDRT/C5
DDRT/C4
DDRT/C3
DDRT/C2
DDRT/C1
DDRT/C0
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in
a LOW state.
Byte 6: Reserve Register
Bit
7
@Pup
Description
1
0
0
0
0
0
0
0
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
6
5
4
3
2
1
0
Byte 7: Dial-a-Frequency Control Register N
Bit
7
@Pup
Name
Description
0
0
0
0
0
0
0
0
Reserved
N6, MSB
N5
Reserved for device function test.
6
These bits are for programming the PLL’s internal N register. This
access allows the user to modify the CPU frequency at very high
resolution (accuracy). All other synchronous clocks (clocks that
are generated from the same PLL, such as PCI) remain at their
existing ratios relative to the CPU clock.
5
4
N4
3
N3
2
N2
1
N1
0
N0, LSB
Rev 1.0,November 20, 2006
Page 7 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
