CY28347
AC Parameters (continued)
66 MHz
100 MHz
133 MHz
200 MHz
Min. Max. Unit
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Notes
P4 Mode CPU at 0.7V
TDC
CPUT/C Duty Cycle
45
14.85
175
55
45
55
45
55
45
4.85
175
55
5.1
700
% 5,6,10,14,15
ns 5,6,10,14,15
ps 15,16
TPeriod
Tr/Tf
CPUT/C Period
15.3
700
9.85
175
10.2
700
7.35
175
7.65
700
CPUT/C Rise and Fall
Times
Rise/Fall Matching
20%
125
100
20%
125
100
20%
125
100
20%
125
100
16,17
Delta Tr/Tf Rise/Fall Time Variation
ps 10,15,16,18
TSKEW
CPUT/C to CPUCS_T/C
Clock Skew
ps 10,11,12,14,1
5
TCCJ
CPUT/C Cycle-to-Cycle
Jitter
150
430
150
430
150
430
150
ps 6,10,11,12,14,
15
Vcross
Crossing Point Voltage
280
280
280
280
430 mV 15.
P4 Mode CPU at 1.0V
TDC
CPUT/C Duty Cycle
45
14.85
175
55
45
55
45
55
45
4.85
175
55
5.1
467
% 5,10,6,14
TPeriod
CPUT/C Period
15.3
467
9.85
175
10.2
467
7.35
175
7.65
467
nS 5,10,6,14
ps 10,11,19
Differ-
ential Tr/Tf Times
CPUT/C Rise and Fall
Delta Tr/Tf Rise/Fall Time Variation
125
100
125
100
125
100
125
100
ps 10,18
TSKEW
CPUT/C to CPUCS_T/C
Clock Skew
ps 10,11,12,14
TCCJ
CPUT/C Cycle-to-Cycle
Jitter
150
150
150
150
ps 10,11,12,14
Vcross
SE-
Crossing Point Voltage
Absolute Single-ended
510
760
325
510
760
325
510
760
325
510
760 mV 19
325
ps 20
DeltaSlew Rise/Fall Waveform
Symmetry
K7 Mode
TDC
CPUOD_T/C Duty Cycle
CPUOD_T/C Period
45
14.85
2.8
55
45
9.85
2.8
55
45
7.35
1.67
0.4
55
45
4.85
2.8
55
% 5,6,10
ns 5,6,10
ns 5,6,10
ns 5,10,21
TPeriod
TLOW
Tf
15.3
10.2
7.65
5.1
CPUOD_T/C LOW Time
CPUOD_T/C Fall Time
0.4
1.6
0.4
1.6
1.6
0.4
1.6
TCCJ
CPUOD_T/C
Cycle-to-Cycle Jitter
250
250
250
250 ps 6,10
VD
VX
Differential Voltage AC
.4
Vp+.6V
1100
.4
Vp+.6V
1100
.4
Vp+.6V
1100
.4
Vp+.6V V 22
1100 mV 23
Differential Crossover
Voltage
500
500
500
500
Chipset
TDC
CPUCS_T/C Duty Cycle
45
55
45
55
45
55
45
55
% 5,10,6
Notes:
14. Measured at VX between the rising edge and the following falling edge of the signal.
15. Determined as a fraction of 2*(Trise-Tfall)/(Trise+Tfall).
16. See figure 6 for 0.7V loading specification.
17. Measurement taken from differential waveform, from -0.35V to +0.35V.
18. The time specified is measured from when all VDD’s reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within
specifications.
19. Ideally the probes should be placed on the pins. If there is a transmission line between the test point and the pin for one signal of the pair (e.g., CPU), you should
add the same length transmission line to the other signal of the pair (e.g., AGP).
20. Measured in absolute voltage, i.e., single-ended measurement.
21. Probes are placed on the pins, and measurements are acquired at 1.5V for 3.3V signals and at 1.25V for 2.5V, and 50% point for differential signals.
22. Measured at VX, or where subtraction of CLK–CLK# crosses 0 volts.
23. VD is the magnitude of the difference between the measured voltage level on a DDRT (and CPUCS_T) clock and the measured voltage level on its complementary
DDRC (and CPUCS_C) one.
Rev 1.0,November 20, 2006
Page 10 of 21
SPECTRALINEAR [ SPECTRALINEAR INC ]
