CY28301
AC Electrical Characteristics[2] (TA = 0°C to +70°C, VDDQ3 = 3.3V 5%, VDDQ2= 2.5V 5% fXTL = 14.31818 MHz)
66.6-MHz Host
100-MHz Host
133-MHz Host
Parameter
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Notes
PCI
TPeriod
PCI CLK Period
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
ns
ns
ns
ns
ns
ns
ns
4, 7
THIGH
PCI CLK High Time
5
6
TLOW
PCI CLK Low Time
TRISE
PCI CLK Rise Time
TFALL
PCI CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
tpZL, tpZH
tpLZ, tpZH
Output Enable Delay (All outputs)
1.0
10.0
10.0
1.0
10.0
10.0
1.0
10.0
10.0
Output Disable Delay
(All outputs)
1.0
1.0
1.0
tstable
All Clock Stabilization from
Power-Up
3
3
3
ms
Group Skew and Jitter Limits
Skew, Jitter
Measure Point
Output Group
CPU
Pin-Pin Skew Max.
175 ps
Cycle-Cycle Jitter
250 ps
Duty Cycle
45/55
Nom. VDD
2.5V
1.25V
1.5V
1.25V
1.5V
1.5V
1.5V
1.5V
SDRAM
APIC
250 ps
250 ps
45/55
3.3V
250 ps
500 ps
45/55
2.5V
48MHz
3V66
250 ps
500 ps
45/55
3.3V
175 ps
500 ps
45/55
3.3V
PCI
500 ps
500 ps
45/55
3.3V
REF
N/A
1000 ps
45/55
3.3V
Test Point
Output
Buffer
Test Load
Clock Output Wave
T
PERIOD
Duty Cycle
T
HIGH
2.0
1.25
0.4
2.5V Clocking
Interface
T
LOW
T
T
RISE
FALL
T
PERIOD
Duty Cycle
T
HIGH
2.4
1.5
0.4
3.3V Clocking
Interface
T
LOW
T
T
RISE
FALL
Figure 1. Output Buffer
Rev 1.0,November 27, 2006
Page 12 of 13
SPECTRALINEAR [ SPECTRALINEAR INC ]
