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CY28301PVCT 参数 Datasheet PDF下载

CY28301PVCT图片预览
型号: CY28301PVCT
PDF下载: 下载PDF文件 查看货源
内容描述: 频率发生器英特尔(R )集成芯片组 [Frequency Generator for Intel(r) Integrated Chipset]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 13 页 / 168 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28301  
DC Operating Requirements (continued)  
Parameter  
Description  
Input Pin Capacitance  
Xtal Pin Capacitance  
Output Pin Capacitance  
Pin Inductance  
Condition  
Min.  
Max.  
5
Unit  
pF  
Cin  
Cxtal  
Cout  
Lpin  
Ta  
13.5  
22.5  
6
pF  
pF  
0
0
7
nH  
°C  
Ambient Temperature  
No airflow  
70  
AC Electrical Characteristics[2] (TA = 0°C to +70°C, VDDQ3 = 3.3V 5%, VDDQ2= 2.5V 5% fXTL = 14.31818 MHz)  
66.6-MHz Host 100-MHz Host 133-MHz Host  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Unit  
Notes  
CPUCLK  
TPeriod  
Host/CPUCLK Period  
15.0  
5.2  
5.0  
0.4  
0.4  
15.5  
N/A  
N/A  
1.6  
10.0  
3.0  
2.8  
0.4  
0.4  
10.5  
N/A  
N/A  
1.6  
7.5  
1.87  
1.67  
0.4  
8.0  
N/A  
N/A  
1.6  
1.6  
ns  
ns  
ns  
ns  
ns  
4
THIGH  
TLOW  
TRISE  
TFALL  
Host/CPUCLK High Time  
Host/CPUCLK Low Time  
Host/CPUCLK Rise Time  
Host/CPUCLK Fall Time  
5
6
1.6  
1.6  
0.4  
SDRAM  
TPeriod  
SDRAM CLK Period  
10.0  
3.0  
2.8  
0.4  
0.4  
10.5  
N/A  
N/A  
1.6  
10.0  
3.0  
2.8  
0.4  
0.4  
10.5  
N/A  
N/A  
1.6  
10.0  
3.0  
2.8  
0.4  
0.4  
10.5  
N/A  
N/A  
1.6  
ns  
ns  
ns  
ns  
ns  
4
5
6
THIGH  
TLOW  
TRISE  
TFALL  
SDRAM CLK High Time  
SDRAM CLK Low Time  
SDRAM CLK Rise Time  
SDRAM CLK Fall Time  
1.6  
1.6  
1.6  
APIC  
TPeriod  
APIC CLK Period  
60.0  
25.5  
25.3  
0.4  
64.0  
N/A  
N/A  
1.6  
60.0  
25.5  
25.30  
0.4  
N/A  
N/A  
N/A  
1.6  
60.0  
25.5  
25.30  
0.4  
64.0  
N/A  
N/A  
1.6  
ns  
ns  
ns  
ns  
ns  
4
5
6
THIGH  
TLOW  
TRISE  
TFALL  
APIC CLK High Time  
APIC CLK Low Time  
APIC CLK Rise Time  
APIC CLK Fall Time  
0.4  
1.6  
0.4  
1.6  
0.4  
1.6  
3V66  
TPeriod  
3V66 CLK Period  
15.0  
5.25  
5.05  
0.5  
16.0  
N/A  
N/A  
2.0  
15.0  
5.25  
5.05  
0.5  
16.0  
N/A  
N/A  
2.0  
15.0  
5.25  
5.05  
0.5  
16.0  
N/A  
N/A  
2.0  
ns  
ns  
ns  
ns  
ns  
4, 8  
5
THIGH  
TLOW  
TRISE  
3V66 CLK High Time  
3V66 CLK Low Time  
3V66 CLK Rise Time  
3V66 CLK Fall Time  
6
TFALL  
0.5  
2.0  
0.5  
2.0  
0.5  
2.0  
Notes:  
4. Period, jitter, offset, and skew measured on the rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.  
5. The time specified is measured from when V achieves its nominal operating level (typical condition V = 3.3V) until the frequency output is stable and  
DDQ3  
operating within specifications.  
DDQ3  
6. T  
7. T  
8. T  
and T  
are measured as transitions through the threshold region V = 0.4V and V = 2.0V (1 mA) JEDEC specification.  
RISE  
HIGH  
LOW  
FALL ol oh  
is measured at 2.0V for 2.5V outputs, and 2.4V for 3.3V outputs.  
is measured at 0.4V for all outputs.  
Rev 1.0,November 27, 2006  
Page 11 of 13  
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