Da ta
Shee t
(Prelimi nar y)
4.3
Write Protect Operation
Erase and program operations are aborted if WP# is driven low during busy time, and kept low for about
100 ns. Switching WP# low during this time is equivalent to issuing a Reset command (FFh). The contents of
memory cells being altered are no longer valid, as the data will be partially programmed or erased. The
R/B# pin will stay low for t
RST
(similarly to
At the end of this time, the command
register is ready to process the next command, and the Status Register bit I/O6 will be cleared to 1, while I/O7
value will be related to the WP# value. Refer to
for more information on device status.
Erase and program operations are enabled or disabled by setting WP# to high or low respectively, prior to
issuing the setup commands (80h or 60h). The level of WP# shall be set t
WW
ns prior to raising the WE# pin
for the set up command, as explained in
and
Figure 4.2
WP# Low Timing Requirements during Program/Erase Command Sequence
WE#
I/O[7:0]
Valid
WP#
Sequence
Aborted
> 100 ns
September 6, 2012 S34ML01G1_04G1_10
Spansion
®
SLC NAND Flash Memory for Embedded
37
SPANSION [ SPANSION ]
